Chair: John T. Yue, AMD
Vice Chair: Shekhar Khandekar, Level One Communications
The 1996 IRPS Tutorials program offers a unique opportunity for those who are new to the field of reliability physics to gain some focused learning in one day on difficult topics from experts in their field. It also provides an avenue for experienced engineers to refresh their thinking and to exchange technical viewpoints with other experts. Furthermore, the tutorial provides an economical alternative to bringing experts to your plant location.
The tutorial topics selected this year are based on feedback from last year's attendees in order to present the most popular subject matter. Each presenter will spend some time developing the fundamental aspects in each topic, so that new and cross disciplined engineers can easily accomplish their goals of learning the subject.
You are encouraged to register early and indicate your tutorial selection on your advanced registration form so that appropriate room assignments can be made. The tutorial fee entitles each attendee to enroll in two (2) of the half-day courses. The tutorial registration fee is $190 with advanced registration or $210 at the door. Each attendee registered for the tutorial will receive a complete copy of the 1996 IRPS Tutorial Notes at the Symposium registration desk.
TUTORIAL TIMES / LOCATIONS
Monday April 29, 1996
8:00 a.m.--11:30 a.m
Room - - - - - - - - - - TUTORIAL
Wedgewood Ballroom..........1A
Governors Hall...............2
Topaz Room...................3
Senators Hall................4
noon--1:00 p.m.
Trinity Hall ... Hosted Luncheon
1:30--5:00 p.m.
Wedgewood Ballroom..........1B
Governors Hall...............6
Topaz Room...................5
Senators Hall................7
ABSTRACTS
Topic 1A. SEMICONDUCTOR DEFECT RELIABILITY MODELING -- Bob Wood and Don Thompson, IBM Microelectronics, Essex Junction, VT (8:00 a.m. -- 11:30 a.m., Wedgewood Ballroom)
This tutorial describes the basics of predicting defect driven semiconductor "field" reliability. Topics include basic probability, life distributions, and acceleration models applied to actual life test data. Additionally a Burn-In model and sampling statistics will be reviewed with an emphasis on what is a practical defect reliability monitor for current technology.
Topic 1B. SEMICONDUCTOR DEFECT RELIABILITY SCREENING AND MODELING--Arthur J. Wager, IBM Microelectronics, Essex Junction, VT (1:30 p.m. -- 5:00 p.m., Wedgewood Ballroom)
This tutorial will build on the generic product reliability modeling (Topic 1A) and show specific modeling of products after burn-in, voltage, and Iddq screens. Each of those screens will be described. In addition to the more common dynamic voltage screen, an enhanced voltage screen at higher product nominal voltage will be described along with its effectiveness and qualification. The advantages of screening of maverick wafers at wafer final test based on voltage screen and Iddq will be shown.
Topic 2. FUNDAMENTAL ISSUES IN HOT-CARRIER RELIABILITY -- James Chung, Massachusetts Institute of Technology, Cambridge, MA and Peng Fang, Advanced Micro Devices, Sunnyvale, CA (8:00 a.m. - 11:30 a.m., Governors Hall)
This tutorial will cover the basics of the hot-carrier degradation mechanisms and their impact on MOS device design and technology. The major hot-carrier mechanisms and accelerated lifetime prediction models will be reviewed. Hot-carrier reliability test structures and characterization techniques will also be overviewed. Key issues in defining ac vs dc hot-carrier lifetime criteria will be explored.
Topic 3. RELIABILITY CHALLENGES AND TRENDS IN DEEP SUBMICRON TECHNOLOGY -- John Sweeney, Motorola, Austin, TX (8:00 a.m. -- 11:30 a.m., Topaz Room)
This tutorial describes reliabilityissues in process integration, characterization techniques to determine their various mechanisms, and process/design approaches to reduce their severity and meet yield and reliability objectives. The tutorial begins with a review of technology trends and integration issues. This is followed by a discussion of important reliability "detractors" (or trade offs) in DRAM, logic, SRAM, and analog applications.
Topic 4. FAILURE ANALYSIS TECHNIQUES -- Larry Wagner, Texas Instruments, Inc., Dallas, TX, Matt Thayer, Advanced Micro Devices, Austin TX, and Paul Winer, Intel Corporation, Santa Clara, CA (8:00 a.m. - 11:30 a.m., Senators Hall)
This tutorial describes classical as well as advanced failure analysis techniques used in analysis of microelectronics devices. Topics covered will be the evolution and application of classical techniques as they apply to submicron devices today. Focused ion beam (FIB) technology is essential to the support of in-line defect characterization, process evaluation and design layout modification. The tutorial will review theory, applications, alternative techniques and technology trends through the use of examples and descriptions which give the attendee a practical understanding of the FIB technology. The electron beam (e-beam) technology is the primary tool of choice for all leading edge circuit probing on submicron silicon. Recent advances have made it possible to integrate high speed testers and CAD based navigation technology.
Topic 5. MECHANICAL PROPERTIES & ELECTROMIGRATION RELIABILITY IN ALUMINUM-BASED INTERCONNECT SYSTEMS-- John E. Sanchez, Jr., University of Michigan, Ann Arbor, MI and Paul R. Besser, Advanced Micro Devices, Sunnyvale CA (1:30 p.m. -- 5:00 p.m., Topaz Room)
The fundamental aspects associated with mechanical stresses and reliability in Al-based interconnect materials' systems are reviewed. The constraints due to substrates and dielectric coatings, which impose thermal and reaction strains and stresses, are reviewed for both continuous films and patterned lines. In addition, the basic phenomena of electromigration and stress-induced voiding are reviewed. Finally, material choices, which may be used in the design of interconnect systems for optimal manufacturing yield, interconnect performance and reliability, are described.
Topic 6. OXIDE RELIABILITY -- Elyse Rosenbaum, University of Illinois, Urbana, IL and Hsing-Huang Tseng, Motorola, Austin, TX (1:30 p.m. -- 5:00 p.m., Governors Hall)
Gate oxide that is subject to electrical stress may suffer from degradation and breakdown. In this tutorial, we will explore the physical causes of oxide wear-out. The entire process flow has an impact on the resilience of gate oxide to this damage. Methods for fabricating robust gate dielectrics, such as CVD stacked oxide and N2O oxynitride, will be presented. We will review process monitoring of intrinsic gate oxide reliability and defect density. Sources of process-induced damage of gate oxide will be discussed, covering both front-end and back-end processes.
Topic 7. PACKAGE TECHNOLOGY -- Suresh Golwalkar, Intel Corporation, Folsom, CA, Jack T. McCullen, Intel Corporation, Chandler, AZ, and Tom M. Moore, Texas Instruments, Inc., Dallas, TX (1:30 p.m. -- 5:00 p.m., Senators Hall)
This presentation reviews trends in both package and silicon technologies which affect package reliability. It includes a discussion of evolving package technology leading to potential reliability concerns associated with new materials, reduced dimensions, additional interfaces, and package interactions with new silicon technologies and end user manufacturing processes. We describe, with examples and models, the main thermal, thermomechanical, and thermochemical mechanisms, and how they interact with package and silicon technology trends.