Chair: Richard A. Wachnik, IBM
Co-Chair: Bernard M. Pietrucha, AT&T
Ten workshops covering important topics in reliability physics are available to all symposium registrants. Moderators will discuss topics of current interest and the attendees are expected to participate. The attendees are encouraged to prepare questions or bring data on related topics which they wish to bring up for discussion. Overhead projectors will be available in the meeting room.
Please note that the workshops will be held on Monday evening after the tutorials. Please register for the workshop of your choice when you register at the conference. The topics and moderators are listed below. For further information contact Bernie Pietrucha (phone: 201-386-4730, fax: ...4147, email: bmp@fuwutai.att.com) or Rick Wachnik (phone: 914-892-2611, fax: ...3039, email: wachnik@fshvmfkl.vnet.ibm.com).
Workshop 1. FIB USER'S GROUP: NEW AND CURRENT ISSUES AND APPLICATIONS OF FOCUSED ION BEAM TECHNOLOGY.
Moderators - Marsha Abramo, IBM; Steve Kirch, Intel
New and current issues for FIB and applications to failure analysis and circuit repair will be discussed. Participants are urged to contact the moderators prior to the workshop and offer to discuss recent work (M. Abramo 802-769-1737; S. Kirch 802-765-5279)
Workshop 2. DIELECTRIC RELIABILITY: E VS 1/E VS OTHER MODELS.
Moderators: Dave Dumin, Clemson; Klaus Schuegraf, Micron; Ed Cartier, IBM
Discussion will focus on fundamental phenomena in time dependant dielectric breakdown in silicon dioxide and the models which have been proposed to describe the dependance of lifetime on voltage, thickness and other parameters. Topics will include stress induced leakage currents, trap generation and detection, electron injection and transport, hole currents, wearout of the dielectric and supply voltage concerns..
Workshop 3. HOT-CARRIERS: DEVICE AND CIRCUIT MODELS.
Moderators: Wilfried Haensch, Siemens; Boon-Khim Liew, TSMC; Toshiaki Tsuchiya, NTT
Discussion will focus on device and circuit models of hot carrier reliability and how they enable reliability to be designed into products and technologies. Device models based on fundamental mechanisms offer the opportunity to optimize device design for maximum reliability. Models usable by circuit designers offer the opportunity to optimize circuit function to improve the reliability of integrated circuits.
Workshop 4. METAL MIGRATION: MECHANISM, MICROSTRUCTURE, AND TEXTURE.
Moderators: Rod Augur, Philips; Ken Rodbell, IBM; Carl Thompson, MIT
Discussion will focus on how understanding of mechanism, microstructure and texture offer opportunities to build in reliability into integrated circuit metallization. The role of grain boundary and interfacial diffusion and how it changes with dimension, deposition, blocking boundaries, and interlayers will be covered.
Workshop 5. PACKAGING: BALL GRID ARRAY PACKAGING.
Moderators: Steve Groothuis, Texas Instruments; Luu Nguyen, National Semiconductor
Discussion will focus on issues with ball grid array packaging using different ceramic and plastic substrates. Stress, thermal mismatch, fatigue, and process issues will be covered.
Workshop 6. Failure Analysis I: Best Practices.
Moderators: Mike Cairns, Motorola; Don Staab, Tandem; Mike Strizich, Analytical Solutions
Discussion will focus on the best practices common problems confronted by failure analysis engineers. This will include localizing fails from test data, deprocessing packages and chips and determining root cause.
Workshop 7. FAILURE ANALYSIS II: CASE STUDIES USING NOVEL TECHNIQUES.
Moderators: Dan Barton, Sandia; Mauro Ciappa, Swiss Fed. Inst. of Tech.; Scott Wills, BEAM IT
Discussion will focus on case studies of failure analyses employing novel or unusual techniques and/or unusual materials. Participants are urged to bring examples for discussion.
Workshop 8. PRODUCT RELIABILITY: TEST, BURN-IN & DEFECTS.
Moderators: Andre Forcier, IBM; Glenn Shirley, Intel; Nick Lycoudes, Motorola
The control of defects using testing of partially processed wafers, functional sort and burn-in permits control of the reliability of outgoing product. Discussion will focus on the product reliability and defect reliability modeling tutorial which occurs during the morning and afternoon prior to workshop.
Workshop 9. WAFER LEVEL TESTING.
Moderators: Michael Dion, Harris; Tim Turner, TET
Wafer level testing has a goal of determining reliability at lower levels of assembly or integration. Discussion will focus on the implementation of wafer level test techniques in laboratory and manufacturing environments.
Workshop 10. RELIABILITY OF HETEROJUNCTION BIPOLAR TRANSISTORS IN WIRELESS TELECOMMUNICATIONS.
Moderators: Peter Ersland, M/A-COM; Dave O'Brien, Hewlett-Packard; Paul Ratazzi, Rome Labs
High performance compound semiconductor devices have enabled the wireless telecommunications industry to expand rapidly. Discussion will focus on failure mechanisms in HBTs and optoelectronic devices used in wireless telecommunications.