TECHNICAL PROGRAM

Tuesday, April 8, 8:15 a.m., Grand Ballroom A, B, & C

SYMPOSIUM OPENING:
Ajit K. Goel , Symposium General Chair
Alan G. Street, Technical Program Chair

SESSION 1: DEVICE AND PROCESS

Co-Chairs: Wagdi W. Abadeer, IBM Microelectronics and
Tim R. Rost, Texas Instruments, Inc.

1.1 Keynote (Invited): SEMICONDUCTOR PROCESS EQUIPMENT RELIABILITY PERSPECTIVE
A.K. Sinha, President, CVD Product Business Group, Applied Materials

1.2 GATE STACK RELIABILITY IMPROVEMENTS USING CONTROLLED AMBIENT PROCESSING
K. Schuegraf, R.P.S. Thakur and R. Weimer, Micron Technology, Boise, ID

This paper investigates the impact of ambient control in critical front-end processes. Gate-oxide reliability improvements and device implications for advanced submicron processes are described. Such processing limits exposure of wafers to cleanroom air and promises reliability improvements, particularly where bare silicon or critical films are present on the wafer surface. Specifically, the benefits of environmental control between gate pre-clean and gate oxidation, gate oxidation and polysilicon deposition. and silicide deposition and annealing are presented.

1.3 SCALING DOWN OF TUNNEL OXYNITRIDE IN NAND FLASH MEMORY: OXYNITRIDE SELECTION AND RELIABILITIES
J. Kim, Samsung Electronics Co., LTD, Yongin-City, Korea and J.D. Choi, W.C. Shin, D.J. Kim, H.S. Kim, K.M. Mang, S.T. Ahn and O.H. Kwon, Samsung Electronics Co., LTD, Kyungki-Do, Korea

The selection of a manufacturable furnace-grown oxynitride process and reliability issues of the scaled tunnel oxide are examined. As the oxide thickness scales down, tunnel oxynitride enhances the cycling endurance, read life time and program disturbance characteristics in the NAND flash memory compared to the conventional dry oxide.

1.4 IMPACT OF PASSIVATION FILM DEPOSITION AND POST ANNEALING ON THE RELIABILITY OF FLASH MEMORIES
S. Shuto, M. Tanaka, M. Sonoda, T. Idaka, K. Sasaki and S. Mori, Toshiba Corporation, Kawasaki, Japan

This paper for the first time, presents the impact of the passivation film deposition on the reliability of the tunnel oxide in various flash memory cells. The electron trap density in the tunnel oxide strongly depends on the refractive index of P-SiON passivation film. This result indicates that there is a correlation between the water resistibility of the passivation film and the tunnel oxide degradation induced by passivation film deposition process. Moreover, the effect of post annealing after passivation film deposition is discussed. The electron trap density is increased at the beginning and then decreased during post-annealing. This time constant strongly depends on the refractive index of the passivation film. We propose the water related electron trap model to explain the results

1.5 CHARACTERIZATION AND MODELING OF A HIGHLY RELIABLE METAL-TO-METAL ANTIFUSE FOR HIGH-PERFORMANCE AND HIGH-DENSITY FIELD-PROGRAMMABLE GATE ARRAYS
C.-C. Shih, R. Lambertson, F. Hawley, F. Issaq, J. McCollum and E. Hamdy, Actel Corporation, Sunnyvale, CA and H. Sakurai, H. Yuasa, H. Honda, T. Yamaoka and T. Wada, Matsushita, Kyoto, Japan and C. Hu, University of California at Berkeley, Berkeley, CA

Reliability of a new a-Si/dielectric antifuse is characterized and modeled. Conclusions are that unprogrammed antifuse leakage and time-to-breakdown are not only functions of applied voltage but are also functions of stressing polarity and temperature. A novel lifetime model for programmed antifuse incorporating the effects of programming and stress current, ambient temperature, and variation of antifuse resistance with temperature is presented.

1.6 MAXIMUM SAFE REVERSE EMITTER VOLTAGE IN BIPOLAR TRANSISTORS FOR RELIABLE 10 YEAR OPERATION
J. Scarpulla, J. Dunkley, S. Lemke, E. Sabin and M. Young, Silicon Systems, Tustin, CA

A determination of the maximum safe reverse base-emitter stress voltage in bipolar transistors for analog or mixed signal applications is provided. The method uses a physical model for the degradation base current along with process variations to resolve a safe bias conditions to meet 10 year reliability goals.

1.7 CORRELATIONS BETWEEN INITIAL VIA RESISTANCE AND RELIABILITY PERFORMANCE
C.D. Graas, H.A. Le and T.A. Rost, Texas Instruments, Inc., Dallas, TX

Accelerated stressing and electromigration testing were conducted on W-plug via chains and single-via Van der Pauw structures respectively. These populations were chosen to include a wide distribution of initial resistances Ro. The high-end of the Ro distribution exhibited a higher early failure rate and a higher spread in electromigration time-to-fail distribution. Processes which produce tightly controlled time-zero via resistance distributions are more desirable for via reliability.

Tuesday, April 8, 2:00 p.m., Grand Ballroom A, B, & C

SESSION 2: FAILURE ANALYSIS / DIELECTRICS & HOT-CARRIERS

Co-Chairs: Steve Kirch, Intel and John Suehle, NIST

2.1 NEW SCREENING CONCEPT FOR DEEP-SUBMICRON CMOS VLSIs USING TEMPERATURE CHARACTERISTICS OF LEAKAGE CURRENTS IN MOS DEVICE
M. Shimaya, NTT System Electronics Labs, Kanagawa, Japan

We proposed a low temperature standby current (LTSC) screening technique based on the temperature dependence of normal and abnormal leakage current in CMOS LSIs. This technique has a sufficient threshold current margin for the pass/fail criterion and provides effective screening for deep-submicron CMOS LSI.

2.2 USING IDDQ DRIFT TESTING TO DETECT HYDROGEN IN MOS DEVICES
E. Sabin, Silicon Systems, Santa Cruz, CA

Time dependent IDDQ testing showed a drift for die with excessive hydrogen in the ILD stack. Hydrogen compensation of boron is proposed to explain this drift. Triangular voltage sweep and bias temperature stress testing found <5E9 mobile ions/cm3, which is not enough to explain the observed drift.

2.3 FOCUSED-ION BEAM-INDUCED INSULATOR DEPOSITION AT DECREASED BEAM CURRENT DENSITY
M. Abramo, E. Adams, M. Gibson and L. Hahn, IBM Microelectronics, Essex Junction, VT and A. Doyle and D. Stewart, Micrion Corp., Peabody, MA

Increasing complexity of VLSI devices has led to the need for an FIB-deposited insulator material with improved dielectric integrity. This paper reviews a method that increases the yield of deposited film per incident ion by decreasing the current density of the ion beam. Both electrical and chemical analyses of these films will be presented.

2.4 EFFECTS OF FOCUSED ION BEAM (FIB) IRRADIATION ON MOS TRANSISTORS
A. Campbell, K. Peterson, J. Soden and D. Fleetwood, Sandia National Laboratories, Albuquerque, NM

Focused ion beam (FIB) modification and imaging of MOS transistor parameters produce shifts in VTH, mobility, and transconductance, depend on ion dose and transistor geometry, and are reduced by electron flood charge neutralization. Recovery occurs with annealing at 150 ºC. These observations are consistent with FIB charge-induced creation of interface traps in the transistors.

2.5 DEGRADATION IN (Ba,Sr) TiO3 THIN FILMS UNDER DC AND DYNAMIC STRESS CONDITIONS
T. Horikawa, T. Kawahara,
M. Yamamuka and K. Ono, Mitsubishi Electric Corporation, Amagasaki, Japan

The reliability of high dielectric constant CVD-deposited films of (Ba,Sr) TiO3 was studied under DC and pulsed conditions. The degradation and breakdown of these films are enhanced by the dielectric relaxation current during bipolar stress, but not during DC stress. The dielectric loss of the films also affects breakdown

2.6 CHARGE TRAPPING AND DEGRADATION OF HIGH PERMITIVITY TiO2 DIELECTRIC MOSFETs
H.-S. Kim, D.C. Gilmer and S.A. Campbell, University of Minnesota, Minneapolis, MN

Alternative dielectrics with high dielectric constants for use in deeply scaled MOSFETs have small bandgaps, with corresponding reliability concerns. Here, the reliability of 190Å TiO2 layers, deposited by metal-organic CVD, are studied. Techniques used include ramped voltage breakdown, time dependent dielectric breakdown, I-V, and C-V measurements.

2.7 CHARACTERIZATION OF BITLINE STRESS EFFECTS ON FLASH CELL AFTER PROGRAM/ERASE CYCLE
Y.-C. Liu, J.C. Guo, K.L. Chang, C.I. Huang, M.T. Wang, A. Chang and F. Shone, Macronix International Co., Hsin-Chu, Taiwan

The impact of bitline stress on the unselected Flash EPROM memory cell during program/erase cycling is investigated considering the accentuated generation of oxide trap charges and interface states. This oxide damage dramatically alters the channel hot carrier characteristics of the devices inducing a severe read disturb condition.

2.8 HOT CARRIER SELF CONVERGENT PROGRAMMING METHOD FOR MULTI-LEVEL FLASH CELL MEMORY
P. Candelier, CEA LETI DMEL PIT, Grenoble, France and F. Mondon, University of J. Fourier, Grenoble, France and B. Guillaumot, SGS Thomson, Grenoble, France and G. Reimbold, H. Achard, F. Martin and J. Hartmann, CEA LETI DMEL PIT, Grenoble, France

Flash EEPROM multi-level programming requires accurate control of programmed threshold voltages. A new hot carrier convergent programming method is proposed to reduce both Vth dispersion and write-erase window closure during endurance test. Feasibility and improved reliability is demonstrated for a four level storage on 0.35 µm Flash cells.

Tuesday April 8, 6:00 -- 6:50 p.m., Hotel Entrance
BUSES TO MUSEUM

Tuesday April 8, 6:30 -- 9:30 p.m.
SYMPOSIUM RECEPTION
MUSEUM OF NATURAL HISTORY

Wednesday April 9, 8:15 a.m., Grand Ballroom D & E

SESSION 3A: PACKAGING (Parallel Session A)

Co-Chairs: Kris Mohan, National Semiconductor and
Thomas M. Moore, Texas Instruments, Inc.

3A.1 TEMPERATURE CYCLING & THERMAL SHOCK FAILURE RATE MODELING
R. Blish II, Advanced Micro Devices, Sunnyvale, CA

The Coffin-Manson formula and lognormal distributions are used to model Thin Film Cracking (TFC) and several other failure mechanisms. The Coffin Manson exponent is found to lie in one of four relatively narrow ranges: progressive crack propagation/arrest ~1.0; ductile metal fatigue ~2; IC metals & intermetallics ~3-5; brittle fracture ~6-7.

3A.2 DEVICE DEGRADATION DUE TO STUD BUMPING ABOVE THE MOSFET REGION AND THE EFFECT OF ANNEALING ON THE DEGRADATION
N. Shimoyama, K. Machida, M. Shimaya, H. Akiya and H. Kyuragi, NTT System Electronics Labs, Kanagawa, Japan

Stud bumping above the MOSFET region generates an interface trap at the Si/SiO2 interface that results in the degradation of mutual-conductance and is apparently recovered by both N2 and H2 annealing. The stronger hot-
carrier tolerance of H2 annealing than N2 annealing is explained by terminating dangling bonds with hydrogen atoms.

3A.3 FLIP CHIP UNDERFILL RELIABILITY OF CSP DURING IR REFLOW SOLDERING
Y. Ohshima, Toshiba Co., Yokohama, Japan and T. Nakazawa, K. Doi, H. Aoki and Y. Hiruta, Toshiba Co., Yokohama, Japan

Reliability of flip chip CSP was investigated. The underfill resin for CSP has a high saturation content of moisture, compared to a conventional mold resin. The IR reflow test showed no delamination and no cracking in the flip chip CSP at the JEDEC level 1 and 2 conditions.

3A.4 RELIABILITY OF HIGH ASPECT RATIO PLATED THROUGH HOLES (PTH) FOR ADVANCED PRINTED CIRCUIT BOARD (PCB) PACKAGES
H. Azimi, K.P. Chong, D. Goyal and M.-J. Lii, Intel Corporation, Chandler, AZ

Thermo-mechanical stresses mainly due to mismatch in the out-of-plane (z-direction) coefficient of thermal expansion can result in the failure of the PTHs. PTH failure may be caused by fracture of the plating material at the barrel, fracture at the land-barrel junction, or delamination of the plating from the PWB.

3A.5 A STUDY OF SEPARATION OF SUPERIMPOSED ULTRASONIC PULSE ECHO SIGNALS FOR SEMICONDUCTOR FAILURE ANALYSIS USING SCANNING ACOUSTIC TOMOGRAPHY (SAT)
H.-S. Jang, Anam Industrial Co., Ltd., Seoul, Korea and K.-Y. Jhang, Hanyang University, Seoul, Korea

Ultrasonic inspection of the die bottom to die attach adhesive interface for thin die has proven difficult as the reflected signals from the die top and bottom are superimposed. In this study, a transfer function technique is used to separate the reflected die bottom signal from the superimposed signal.

3A.6 CHARACTERIZATION OF FLIP CHIP INTERCONNECT FAILURE MODES USING HIGH FREQUENCY ACOUSTIC MICRO IMAGING WITH CORRELATIVE ANALYSIS
J. Semmens and L.W. Kessler, Sonoscan, Bensenville, IL

New methods for the analysis of flip chip solder interconnects use acoustic micro imaging to analyze the solder joint through the entire thickness of the solder ball at the solder/substrate interface. Laminar cracks under the bond pad and in the surrounding glassivation layers on the silicon die were detected.

3A.7 TOWARDS A NONDESTRUCTIVE PROCEDURE FOR COMPONENT LEVEL CHARACTERIZATION OF MOLDING COMPOUNDS
S. Canumalla and L.W. Kessler, Sonoscan, Bensenville, IL

A nondestructive inspection procedure is described for characterizing molding compounds. The velocity and attenuation of ultrasound in the molding compound are investigated in this study for commercial molding compounds based on a) bisphenol and b) creosol novolac. In situ measurements on commercial packages indicate that different molding compounds have different ultrasonic signatures. Variations within the same package can also be mapped using this technique.

Wednesday, April 9, 8:15 a.m., Grand Ballroom A, B, & C

SESSION 3B: DIELECTRICS (Parallel Session B)

Co-Chairs: William R. Hunter, Texas Instruments, Inc. and
William M. Miller, Sandia National Laboratories

3B.1 EVIDENCE OF ELECTRON-HOLE COOPERATION IN SiO2 DIELECTRIC BREAKDOWN
H. Satake, S.-i. Takagi, and A. Toriumi, Toshiba, Kawasaki, Japan

Using substrate hot hole injection, the roles of hot electrons and holes for dielectric breakdown of SiO2 have been investigated, by separately controlling the amounts of injected electrons and holes. It is shown that the coexistence of both injected electrons and holes is essential for the dielectric breakdown.

3B.2 INVESTIGATION OF OXIDE CHARGE TRAPPING AND DETRAPPING IN A n-MOSFET
T. Wang, T.E. Chang, L.P. Chiang and N.K. Zous, National Chiao-Tung University, Hsin-Chu, Taiwan and C. Huang, Macronix International Co., Hsin-Chu, Taiwan

Oxide hole and electron trapping/detrapping in a n-MOSFET were investigated by monitoring the temporal evolution of GIDL current. The field dependence of the charge detrapping time indicates that trapezoidal barrier tunneling is a major mechanism in both hole and electron detrapping. A trap assisted sequential tunneling model was used for hole detrapping.

3B.3 ACCELERATED GATE-OXIDE BREAKDOWN IN MIXED VOLTAGE I/O CIRCUITS
T. Furukawa, D. Turner, S. Mittl, M. Maloney, R. Serafin, W. Clark, J. Bialas, K. Longenbach and J. Howard, IBM Microelectronics, Essex Junction, VT

In real, mixed voltage I/O products, Fowler-Nordheim testing does not adequately predict gate oxide lifetime. Unexpected gate-oxide failures are attributed to non-conductive channel hot-electron injection at the drain edge.

3B.4 THE EFFECTS OF NITROGEN IMPLANT INTO GATE ELECTRODE ON THE CHARACTERISTICS OF DUAL-GATE MOSFETS WITH ULTRA-THIN OXIDE AND OXYNITRIDES
A. Chou, C. Lin, K. Kumar, P. Chowdhury, M. Gardner*, M. Gilmer*, J. Fulford*, and J. Lee, University of Texas, Austin, TX
*AMD, Austin, TX

The effects of nitrogen implant conditions, gate dielectric, gate microstructure, and gate dopant species on the characteristics of ultra-thin gate oxide MOSFETs is investigated. In addition to reducing boron penetration in p+ pMOSFETs, N implantation improves oxide quality, but at the expense of increased polysilicon depletion.

3B.5 IMPACTS OF PLASMA PROCESS-INDUCED DAMAGE ON ULTRA-THIN GATE OXIDE RELIABILITY
K. Eriguchi, T. Yamada, Y. Kosaka and M. Niwa, Matsushita Electric Ind. Co., Ltd., Osaka, Japan

The leakage current induced by plasma charging damage is characterized from the time dependence of this current under constant voltage stress. A quantitative evaluation method of plasma-induced damage is proposed. It is also found that annealing recovers only the plasma-induced traps, not the Si/SiO2 interface states.

3B.6 DETERMINATION OF ULTRA-THIN OXIDE VOLTAGE THICKNESS AND ITS IMPACT ON OXIDE RELIABILITY PROJECTION
E.Y. Wu, S.-H. Lo*, W.W. Abadeer, A. Acovic**, D. Buchanan*, T. Furukawa, D. Brochu, and R. Dufresne, IBM Microelectronics, Essex Junction, VT
*IBM Research Center, Yorktown Heights, NY
**EM Microelectronics Marin, Marin, Switzerland

Ultra-thin oxide thickness and voltage were accurately determined by a modified quantum interference technique and Berglund C-V integration in both accumulation and inversion. Experimental results show excellent agreement with theoretical calculations including substrate quantization and polysilicon depletion. The impact of these results on ultra-thin oxide reliability projection will be discussed.

3B.7 OXIDE BREAKDOWN MECHANISM AND QUANTUM PHYSICAL CHEMISTRY FOR TIME-DEPENDENT DIELECTRIC BREAKDOWN
M. Kimura, Mitsubishi Electric Corporation, Hyogo, Japan

The field dependence of long term time-dependent dielectric breakdown (TDDB) is interpreted using semiempirical molecular orbital calculations based on quantum physical chemistry. The structural transformation from hole-trapped oxide to broken down oxide accounts well for the TDDB phenomenon.

Wednesday, April 9, 2:00 p.m., Grand Ballroom A, B, & C

SESSION 4: METALLIZATION

Co-Chairs: Carole D. Graas, Texas Instruments, Inc. and
John E. Sanchez, Jr. University of Michigan

4.1 EFFECT OF TEXTURE ON ELECTROMIGRATION OF CVD COPPER
C. Ryu, A. Loke, T. Nogami, and S.S. Wong, Stanford University, Stanford, CA

CVD-Cu films were deposited with either (111) or (200) texture and similar grain size distributions, using proper seed layers. The electromigration lifetime of (111) CVD-Cu is about 4 times longer than that of (200) CVD-Cu. The EM activation energy is about 0.8 eV for both types of films.

4.2 A NOVEL ELECTROMIGRATION FAILURE MECHANISM - VIA DELAMINATION
Y.H. Lee, K. Wu, N. Mielke, L.J. Ma, and S. Hui, Intel, Santa Clara, CA

Electromigration-induced via delamination was investigated and understood. This failure mechanism is driven by mass transport, environmental current, thermal, and mechanical stresses. It was eliminated by process enhancements including lowering film stresses and strengthening adhesion at the W-plug/metal and metal/interlevel dielectric interfaces.

4.3 RECENT PROBLEMS IN ELECTROMIGRATION TESTING
B. Baerg, Intel Corporation, Santa Clara, CA

Electromigration testing of advanced interconnects requires specialized structures. Phenomena which must be taken into account include the link-length or threshold current effect, the reservoir effect, extrusions, and via delamination. Four examples of test structures which gave unexpected results as a consequence of these behaviors are discussed.

4.4 CHARACTERIZATION OF CONTACT AND VIA FAILURE UNDER SHORT DURATION HIGH PULSED CURRENT STRESS
K. Banerjee, University of California, Berkeley, CA and A. Amerasekera, and G. Dixit, Texas Instruments, Inc, Dallas, TX and N. Cheung and C. Hu, University of California, Berkeley, CA

Contact and via failure under short duration high current pulses were studied and the mechanisms are presented. The critical current to failure is strongly dependent on the pulse width, and the contact/via size. An understanding of the contact breakdown mechanism was developed to help design more robust advanced interconnects.

4.5 EFFECT OF Al-W INTERMETALLIC COMPOUNDS ON ELECTROMIGRATION IN Al/CVD-W INTERCONNECTS
M. Sekiguchi, M. Yamanaka and S. Mayumi, Matsushita Electric Industrial Co., Ltd, Osaka, Japan

The formation of a W-oxide at the Al/W interface in bilayer Al/CVD-W interconnects allows 10x electromigration lifetime improvements. Activation energy measurements show that Al grain boundary diffusion is suppressed. Detailed microstructural studies show that this is due to the growth of Al-W intermetallic compounds in grain boundaries.

4.6 INFLUENCE OF WATER ABSORPTION OF DIELECTRIC UNDERLAYERS ON Al(111) CRYSTALLOGRAPHIC ORIENTATION in Al-Si-Cu/Ti/TiN/Ti LAYERED STRUCTURES
T. Yoshida, S. Hashimoto, H. Hosokawa, T. Ohwaki, Y. Mitsushima, and Y. Taga, Toyota Central R&D Lab, Aichi, Japan

Al(111) orientation in Al-Si-Cu/Ti/TiN/Ti/dielectric structures was drastically improved by exposing dielectric (BPSG) underlayers to a humid air ambient. The improved orientation was closely related to the amount of water absorbed near the dielectric surfaces. Interconnects fabricated with the improved Al-Si-Cu/Ti/TiN/Ti film showed excellent electromigration lifetimes.

4.7 INTERACTION BETWEEN WATER AND FLUORINE DOPED SILICON OXIDE FILM DEPOSITED BY PECVD
M. Yoshimaru, S. Koizumi, K. Shimokawa and J. Ida, Oki Electric Industry Co., Ltd, Tokyo, Japan

Water absorption characteristics of fluorine-doped PECVD SiO2 films are presented. High fluorine concentration films are more hygroscopic because of a high ratio of silicon difluoride sites to total fluorine bonding sites. Excess He dilution during deposition prevents silicon difluoride sites and lowers both film dielectric constant and water absorption.

Wednesday, April 9, 7:00 -- 8:00 p.m., South Convention Lobby

BANQUET RECEPTION

Wednesday, April 9, 8:00 p.m., Grand Ballroom

AWARDS BANQUET

Thursday, April 10, 8:15 a.m., Grand Ballroom D & E

SESSION 5A: COMPOUND SEMICONDUCTORS AND OPTOELECTRONICS (Parallel Session A)

Co-Chairs: Daniel L. Barton, Sandia National Laboratories and
Sammy A. Kayali, Jet Propulsion Laboratory

5A.1 (Invited ESREF `96 Best Paper) THE EFFECT OF HOT ELECTRON STRESS ON THE dc AND MICROWAVE CHARACTERISTICS OF GaAs-PHEMTS AND INP-HEMTs
R. Menozzi, M. Borgarino, P. Cova, and F. Fantini, University of Parma, Parma, Italy and Y. Baeyens and M. Van Hove, IMEC, Leuven, Belgium

This work reports on hot-electron stress experiments performed on SiN passivated AlGaAs/InGaAs/GaAs pseudomorphic HEMTs and InAlAs/InGaAs/InP lattice-matched HEMTs. We study the effects of the stress on both the device dc and RF characteristics, and investigate their correlation. In both the GaAs and InP HEMTs the high drain bias, room temperature hot-electron stress produces some permanent change of the dc and RF characteristics which can be attributed to charge trapping phenomena.

5A.2 CURRENT-GAIN LONG-TERM INSTABILITY OF AlGaAs/GaAs HBT: PHYSICAL MECHANISM AND SPICE SIMULATION
S. Sheu and J.J. Liou, University of Central Florida, Orlando, FL and C.I. Huang, Wright Patterson AFB, WPAFB, Ohio

The current gain instability of AlGaAs/GaAs heterojunction bipolar transistor (HBT) is investigated, and a new AlGaAs/GaAs HBT model for SPICE circuit simulation is presented. Such a model includes the effects of base and collector leakage currents and the stress-induced abnormal base current, thus allowing the simulation of the performance of HBT circuits subjected to the electrical/thermal stress test (i.e., burn-in test).

5A.3 SCREENING FOR EARLY AND RAPID DEGRADATION IN GaAs/AlGaAs HBTs
T. Henderson and M. Tutt, Texas Instruments, Dallas, TX

We describe a series of pre-stress measurements, including optical inspection, DC parameter tests, electroluminescence, and noise measurements on GaAs/AlGaAs HBTs designed to screen out devices which suffer early failure. A bias stress test on these devices was then performed, and the correlation between lifetime of the devices and the pre-stress tests is determined. For this particular set of devices, optical inspection, DC parameter tests, and electroluminescence showed good correlation, while noise measurements did not.

5A.4 RELIABILITY AND ALLEVIATION OF PREMATURE ON-STATE AVALANCHE BREAKDOWN IN DEEP SUBMICRON POWER PHEMTs
Y.C. Chou and G.P. Li, University of California, Irvine, Irvine, CA and Y.C. Chen, R. Lai and D.C. Streit, TRW, Redondo Beach, CA

The reliability of devices operating at premature on-state avalanche breakdown and a method using a proper electrical stress to alleviate the breakdown are investigated in deep submicron power AlGaAs/InGaAs/GaAs PHEMTs. The results show that depending on the gate and drain biases in device stress, alleviation of premature on-state avalanche breakdown may be achieved without degrading PHEMTs DC and RF performance. On the other hand, PHEMTs may suffer catastrophic failure when stressed at Vds above the threshold value. This study facilitates the useful information for evaluating the reliability constraint imposed by premature on-state avalanche breakdown and highlights a new direction to improve the reliability and power performance of PHEMTs.

5A.5 RAPID DEGRADATION OF InGaAsP/InP LASER DIODE DUE TO COPPER CONTAMINATION
K. Fujihara, M. Ishino and Y. Matsui, Matsushita Electric Industrial Co., Ltd., Osaka, Japan

We have investigated the influence of copper contamination upon rapid degradation of InGaAsP/InP buried heterostructure laser diodes under high stress aging test, for the first time. Strong correlation between the quantity of contaminated copper in the laser diodes and the degradation of lasing characteristics has been confirmed.

5A.6 AN EMPIRICAL LIFETIME PROJECTION METHOD FOR LASER DIODE DEGRADATION
N. Hwang, S.-G. Kang, H.-T. Lee, S.-S. Park, M.-K. Song and K.-E. Pyun, ETRI, Taejon, Korea

An empirical method for lifetime projection of 1.5 µm InGaAs/InP MQW-DFB laser diodes (LD) is presented. On the basis of experimental results of accelerated aging test for 1500 hours, relationship between LD degradation, operating voltage, and ambient temperature has been determined. The presented method makes it possible to predict the lifetime of LDs by determining the thermal voltage ratio.

5A.7 LIFE TESTS AND FAILURE MECHANISMS OF GaN/AlGaN/InGaN LIGHT EMITTING DIODES
D.L. Barton, C.J. Helms and N.H. Berg, Sandia National Laboratories, Albuquerque, NM and M. Osinski and P. Perlin, University of New Mexico, Albuquerque, NM

In order to investigate the reliability of LEDs fabricated in gallium nitride and related materials, a group of twenty Nichia NLPB-500 LEDs were life tested. After 6636 hours only a few failures have been observed. This work reviews the reliability predictions based on the test results, the failure analysis that was performed on the degraded devices, and the degradation mechanisms that were identified.

Thursday, April 10, 8:15 a.m., Grand Ballroom A, B, & C

SESSION 5B: HOT-CARRIER (Parallel Session B)

Co-Chairs: Matt Wordeman, IBM Microelectronics and
Carlos Diaz, Hewlett-Packard

5B.1 NBTI-CHANNEL HOT CARRIER EFFECTS IN ADVANCED SUBMICRON pMOSFETs
G. LaRosa, F. Guarin, S. Rauch, A. Acovic*, J. Lukaitis and E. Crabbe, IBM Microelectronics, Hopewell Junction, NY *EM Microelectronique Marin, Marin, Switzerland

Channel hot-carrier reliability of a 0.35 µm p+ pMOSFET is investigated. In short-channel devices the worst damage is observed at Vg=Vd conditions and is controlled by both negative bias temperature instability and the channel hot carrier mechanism. Both mechanisms form positive fixed charge that explain the observed Vt shifts. Interface trap generation is controlled by hot-hole injection that reduces channel mobility.

5B.2 IMPACT OF BORON PENETRATION ON GATE OXIDE RELIABILITY AND DEVICE LIFETIME IN p+-POLY PMOSFETs
B.Y. Kim, I.M. Liu, H.F. Luan, M. Gardner*, J. Fulford*, and D.L. Kwong, University of Texas at Austin, Austin, TX *AMD, Austin, TX

The effects of boron penetration on gate oxide reliability and device hot-carrier immunity in p+-poly pMOSFETs are studied systematically as a function of drive-in conditions. Both charge trapping and interface state generation are considerably enhanced as a result of boron penetration, significantly degrading p+-poly pMOSFET device lifetime.

5B.3 A NEW TECHNIQUE TO MEASURE AN OXIDE TRAP DENSITY IN A HOT CARRIER STRESSED n-MOSFET
T. Wang, L.P. Chiang, T.E. Chang, N.K. Jous and G.Y. Shen, National Chiao-Tung University, Hsin-Chu, Taiwan and C. Huang, Macronix International Co., Hsin-Chu, Taiwan

Hot-carrier stress generated oxide traps are measured in nMOSFETs using a new sensitive technique. Sub-threshold current is measured during a series of oxide charge detrapping and measurement phases. An analytic model relating a sub-threshold current transient to oxide charge detrapping and oxide trap time constants was derived.

5B.4 A NOVEL METHODOLOGY FOR RELIABILITY STUDIES IN FULLY DEPLETED SOI MOSFETs
S. Banna, P.C.H. Chan, S.S. Wong, S.K.H. Fung and P.K. Ko, University of Science & Technology, Kowloon, Hong Kong

A novel measurement technique is used to independently characterize hot-carrier induced degradation of both the front and back interfaces of a fully depleted SOI MOSFET. Degradation of both interfaces is measured in different Vds ranges, and a model which describes the realistic device degradation is proposed.

5B.5 KEY HOT-CARRIER DEGRADATION MODEL CALIBRATION AND VERIFICATION ISSUES FOR ACCURATE AC CIRCUIT-LEVEL RELIABILITY SIMULATION
W. Jiang, H. Le, S. Dao, S. Kim, B. Stine and J.E. Chung, M.I.T., Cambridge, MA and Y.-J. Wu, P. Bendix, S. Prasad and A. Kapoor, LSI Logic, Milpitas, CA and T. Kopley, T. Dungan, I. Manna and P. Marcoux, Hewlett-Packard, Palo Alto, CA and L. Wu, A. Chen and A. Liu, BTA Technology Inc., Santa Clara, CA

This study provides model calibration and evaluation guidelines to enable more consistent and effective use of hot-carrier reliability simulation tools. Benchmarks verify the accuracy of properly calibrated AC models. SPICE modeling errors, secondary physical mechanisms and statistical parameter variations are found to significantly impact the simulation results.

5B.6 ENHANCEMENT TO HOT-CARRIER INDUCED DEGRADATION UNDER LOW VOLTAGE STRESS DUE TO HYDROGEN FOR NMOSFETS WITH Si3N4 FILMS
S. Tokitoh, H. Uchida,, K. Shibusawa, N. Murakami, T. Nakamura, H. Aoki, S. Yamamoto and N. Hirashita, Oki Electric Industry Co., Ltd., Tokyo, Japan

A new hot-carrier induced degradation mode is described for transistors with SiN on the gate electrode. This degradation is exaggerated by increased hydrogen in the SiN. Hydrogen diffusion from SiN into the gate oxide during high temperature annealing is considered to be the cause of this effect.

5B.7 NEW UNDERSTANDING OF LDD CMOS HOT-CARRIER DEGRADATION AND DEVICE LIFETIME AT CRYOGENIC TEMPERATURES
J. Wang-Ratkovic and R.C. Lacoe, The Aerospace Corporation, Los Angeles, CA and K.P. MacWilliams, Novellus Systems, San Jose, CA and M. Song, AMD, Sunnyvale, CA

We demonstrate that the worst case gate bias condition at 78K is a strong function of the channel length and the drain voltage. This work clarifies the apparent contradiction in the literature concerning worst case hot carrier bias at cryogenic temperatures and further illuminates the effects of device parameters and temperature on lifetime.

Thursday, April 10, 2:00 p.m., Grand Ballroom A, B, & C

SESSION 6: ESD AND LATCHUP

Co-Chairs: Ajith Amerasekera, Texas Instruments and
James W. Miller, Motorola

6.1 SHORT-TIMESCALE THERMAL MAPPING OF INTERCONNECTS
Y. S. Ju and K.E. Goodson, Stanford Univ., Stanford, CA

Scanning laser-reflectance thermometry captures the transient temperature distributions along aluminum interconnects subjected to sub-microsecond current pulses of density exceeding 1E7 A/cm2. The peak temperature distribution depends strongly on the pulse duration and is qualitatively shown to influence the onset location for thermomechanical failure of the interconnect/passivation structures.

6.2 STUDY OF THE 3D PHENOMENON DURING ESD STRESSES IN DEEP SUBMICRON TECHNOLOGIES USING A PHOTON EMISSION TOOL
P. Salome and C. Leroux, CEA LETI DMEL SPIT, Grenoble, France and J.P. Chante, CEGEL Y ECPA-INSA, Villeurbonne, France and P. Crevel, MATRA MHS, Nantes, France

A 3D phenomenon essential for ESD robustness of submicron CMOS technologies is presented and discussed. Gated emission microscopy studies are used to demonstrate in real time, that the current during the ESD event is not instantly uniform. The parameters having an effect on the turn-on are analyzed, and the results lead to an interesting rule for ESD designers.

6.3 STUDY OF A CMOS I/O PROTECTION CIRCUIT USING CIRCUIT-LEVEL SIMULATION
T. Li, D. Suh*, S. Ramaswamy, P. Bendix*,
E. Rosenbaum, A. Kapoor*, and S.M. Kang, University of Illinois at Urbana-Champaign, Urbana, IL
*LSI Logic, Milpitas, CA

Circuit-level simulation is conducted for a two-stage protection circuit. By simulation, we are able to interpret the failure mechanism and identify the failure site. It is demonstrated that circuit-level simulation can accurately describe the protection circuit operation under ESD stress.

6.4 A COMPACT MODEL OF HOLDING VOLTAGE FOR LATCH-UP IN EPITAXIAL CMOS
M.-J. Chen, National Chiao Tung University, Hsinchu, Taiwan R.O.C. and C.-S. Ho, P.-N. Tseng and R.-Y. Shiue, TSMC, Hsin-Chu, Taiwan and K.-L. Jeng and Y.-N. Jou, Vanguard, Hsin-Chu, Taiwan and H.S. Lee and G.H. Chen, National Chiao Tung University, Hsin-Chu, Taiwan

A compact model for predicting latchup holding voltage for different anode-to-cathode spacings and epitaxial thicknesses is presented. A closed-form expression for the holding voltage is given. The model is verified with experimental and simulated data.

6.5 LATCH-UP CHARACTERIZATION OF HIGH ENERGY ION IMPLANTED NEW CMOS TWIN WELLS THAT COMPRISED THE BILL (BURIED IMPLANTED LAYER FOR LATERAL ISOLATION) AND B.L./C.L. (BURIED LAYER/CONNECTING LAYER) STRUCTURE
J.K. Kim, LG Semicon Co., Ltd., Cheongju, Korea and S.-H. Park, W.-S. Yang, Y.-J. Lee and J.-M. Hwang, LG Semicon Co., Ltd., Choong-book, Korea and Y.-K. Sung, Korea University, Seoul, Korea

The characterization of CMOS process using high energy implanted wells has shown the dependence of latchup on the well design. A guideline is proposed for the optimization of the latchup hardness based on process and design parameters.