Chair: Tony Oates, Lucent Technologies
Vice Chair: John Suehle, NIST
The 1997 IRPS Tutorials program offers a unique opportunity for those who are new to the field of reliability physics to gain some focused learning in one day on difficult topics from experts in their field. It also provides an avenue for experienced engineers to refresh their thinking and to exchange technical viewpoints with other experts. Furthermore, the tutorial provides an economical alternative to bringing experts to your plant location.
The tutorial topics selected this year are based on feedback from last year's attendees in order to present the most popular subject matter. Each presenter will spend some time developing the fundamental aspects in each topic, so that new and cross disciplined engineers can easily accomplish their goals of learning the subject.
You are encouraged to register early and indicate your tutorial selection on your advanced registration form so that appropriate room assignments can be made. The tutorial fee entitles each attendee to enroll in two (2) of the half-day courses. The tutorial registration fee is $190 with advanced registration or $240 at the door. Each attendee registered for the tutorial will receive a complete copy of the 1997 IRPS Tutorial Notes at the Symposium registration desk.
Monday April 7, 1997
Room (tentative) - - - - - - Tutorial
8:00 a.m.--11:30 a.m
Majestic Ballroom.....................1
Silver Room............................2
Grand Ballroom A.....................3
Grand Ballroom D/E..................4
Grand Ballroom C.....................5
1:30--5:00 p.m.
Majestic Ballroom..................... 8
Silver Room............................6
Grand Ballroom A.....................9
Grand Ballroom D/E..................7
This tutorial addresses reliability issues that impact device and chip designs. After a brief review of basic reliability concepts, failure mechanisms are described with examples from memory and logic. The physical mechanisms involved are then detailed. Measures to improve reliability are discussed. Failure sources include electrostatic discharge (ESD), electro- and stress-migration, radiation damage, dielectric reliability, hot-carrier effects, latch-up, and burn-in.
Plastic Ball Grid Array (PBGA) presents new challenges in preventing interfacial delamination at the multitude of interfaces that exists. The main areas where efforts have been directed are the attachment reliability, PBGA moisture (i.e., popcorn) performance, component-level solder ball integrity and reliability through typical component-level stress testing. Each of these issues mentioned above will be addressed with a particular emphasis on BGA attachment reliability testing and associated statistical failure distributions and field lifetime predictions. Component qualification data and observations made during the stress testing of a variety of BGA package types will be presented. Lastly, moisture performance testing methods and results will be outlined.
Due to low resistivity and high melting point, copper is the best
candidate for future interconnect material for sub-micron high performance product.
In
this tutorial, we will cover the requirements for an ideal interconnect
for future products, methods for depositing copper interconnects, and the
roles of diffusion barriers. We also review the reliability data on copper
metallurgy. The key issues like Electromigration, Stress Migration, Corrosion
in copper metallization and the Drift/Diffusion of copper in Dielectric will
be presented in details. The process integration issues of copper with the
FEOL and BEOL will also be reviewed.
Plasma charging damage is a serious concern for advanced silicon VLSI manufacturing. It is a problem that will become unavoidable as the industry continue to scale the thickness of the gate oxide. We must learn to minimize charging damage as well as learn to live with it. In this workshop, I will discuss the mechanisms through which charging damage arises. Emphasis will be on simple physical picture that can provide an intuitive feel of the problem. The problem of measurement is complicated and cannot be separated from the physics of gate oxide reliability and device reliability. Many of the measurement techniques will be discussed. The advantage and disadvantage of each one as well as how to use them properly will be covered.
Assuring IC reliability today is a great challenge which can partly be met through wafer level reliability (WLR). Traditional WLR approaches have emphasized test speed over quality of data. We will demonstrate how proper attention paid to the underlying reliability physics can yield WLR which provides quantitative data economically in a short period of time, supporting process monitoring, rapid qualification and reliability tool parameter extraction. We will describe the theoretical approaches needed to maximize the quality of WLR with data examples for electromigration, plasma damage, hot carriers, and oxide integrity. These technical examples will demonstrate the features and utility of WLR when the test methodology is optimized for predictability and not just speed.
This tutorial will cover the current methods and practices for thermal measurements of packaged semiconductor devices, how these measurement and analysis techniques can be used to accurately predict thermal performance. The tutorial will also cover the increasing need for thermal measurements and highlight the need for higher accuracy. Thermal resistance will be explained on a physical basis. This tutorial will educate the student in the proper methods of thermal analysis including, test methods, environmental conditions, board mounting considerations, and application of the data to real world problems.
Oxide breakdown is the sudden loss of the insulating properties of a thin oxide layer subject to an electric field. Two main issues make this reliability problem complex : 1) the oxide field dependence of breakdown is still an open question, and 2) the time-to-breakdown is a statistically distributed parameter. In this tutorial, these two aspects will be treated starting from an overview of the present day physical understanding of the oxide degradation and breakdown process. A comparison between the several models that coexist in literature will be made. Finally, the experimental and theoretical difficulties of predicting oxide reliability at low field (= real operation conditions of devices) will be discussed.
This tutorial describes several failure analysis techniques for localizing defects on complex integrated circuits. The topics covered include Resistive Contrast Imaging (RCI) for stressed conductor localization on test structures, Charge-Induced Voltage Alteration (CIVA) and Low Energy CIVA (LECIVA) for open conductor localization on state-of-the-art integrated circuits, Light-Induced Voltage Alteration (LIVA) for backside defect localization and transistor logic state determination, infrared light emission microscopy for increased sensitivity and backside examination, and Fluorescent Microthermal Imaging (FMI) for localization of heat generating defects with high spatial and thermal resolution. For each technique we discuss the physics of signal generation, the system requirements for implementation, the technique's limitations, and examples showing how the technique was applied in failure analysis.
In this tutorial a review of hot electron effects relating to the physics and reliability in MOSFETs and other semiconductor devices will be given. The main areas surveyed are : (i) history of hot electron effects, (ii) the mechanisms of hot electron (hole) degradation, (iii) Monte Carlo hot electron transport simulation technique, and (iv) the discovery and the theory of the giant isotope effect of hydrogen (deuterium) desorption initiated by channel hot electrons and scanning tunneling microscopy. Finally, hydrogen (deuterium) desorption theories based on local density functional computations will be combined with Monte Carlo simulations of hot electron transport to construct a precise numerical formalism to describe hot electron damage in NMOS transistors