Tuesday, March 31, 8:15 a.m., Reno Ballroom

SYMPOSIUM OPENING:

The Reliability Challenge: New Materials in the New Millenium—J. S. England and R.W. England, Texas Instruments, Dallas, TX

Moore's Law has driven phenomenal growth in the semiconductor industry. Now, for that law to continue, a discontinuity in basic semiconductor materials is underway. The materials on which we have based our careers are giving way to new interlevel and memory storage dielectrics, and copper metallization. Given the size and economic impact of our industry on the global economy, accelerated understanding of the new materials properties and physics of failure is a must. This paper deals with the work environment, skills and tools required for the reliability scientist to prepare the semiconductor industry for the new millennium.

1.1 (invited) MEMS: A Whole New World of Capabilities; A  Whole New World of Reliability Issues—R.S. Payne, Cyrano Sciences Corporation, Santa Clara, CA

The inertial measurement devices that have been enabled by Micro-Electro-Mechanical Systems (MEMS) have or will revolutionize the measurement and control of the motion that surrounds our everyday life. The integration of moving parts with micron scale dimensions into electronic systems has and will open the door to new reliability science as well. This talk will try to excite your curiosity.

1.2 Lifetime Estimates and Unique Failure Mechanisms of the Digital Micromirror Device (DMD)—M.R. Douglass, Texas Instruments, Plano, TX

The Digital Micromirror Device (DMD) has experienced improvements in both performance and reliability. Each device consists of over 500,000 individually addressable micromirrors and has been used in such products as film-like projectors and printers. Reliability testing has demonstrated greater than 100,000 operating hours and over 1 trillion mirror cycles.

1.3 How MicroElectroMechanical Systems (MEMS) Fail—S.L. Miller, M.S. Rodgers, G. LaVigne, J.J. Sniegowski, D.M. Tanner, and K.A. Peterson, Sandia National Laboratories, Albuquerque, NM

We identify failure modes common to a broad range of advanced MEMS actuators and sensors, and present demonstrated methods to mitigate them. This is done by performing operational characterization of devices designed and fabricated using advanced technologies with which many future systems are likely to be created.

1.4 The Effect of Frequency on the Lifetime of a Surface Micromachined Microengine Driving a Load—D.M. Tanner, W.P. Eaton, N.F. Smith, D. Bowman, P. Tangyunyong, K.A. Peterson, and W.M. Miller, Sandia National Laboratories, Albuquerque, NM

We performed experiments on surface micromachined microengines driving load gears to determine the effect of rotational frequency on the median life to failure. The results, which are somewhat counterintuitive, indicate that parts operated at 90,000 rpm fail with less accumulated cycles than parts at 180,000 rpm.
 

1.5 Enhanced Dielectric Breakdown Lifetime of Copper/Silicon Nitride/Silicon Dioxide Structure—K. Takeda, K. Hinode, Hitachi, Ltd., Tokyo, Japan, I. Oodake, Hitachi, Ltd., Saitama, Japan, N. Oohashi and H. Yamaguchi, Hitachi, Ltd., Tokyo, Japan

Time-dependent dielectric breakdown of Cu/(SiN and/or SiO₂)/(Si or Cu) capacitors is investigated. The dielectric breakdown lifetime only depends on the electric field strength of dielectrics in contact with the Cu anode and does not depend on the thickness or the structure (single-layer/multilayer) of the dielectrics. The layered SiN/SiO₂ structure has higher dielectric breakdown resistance than a monolayer structure (SiN, SiO₂). This is because of the low electric-field strength of SiN caused by high dielectric constant.

1.6 Switching behavior of the Soft Breakdown Conduction Characteristic in Ultra-thin (<5 nm) Oxide MOS Capacitors—E. Miranda, J. Sune, R. Rodriguez, M. Nafria, and X. Aymerich, Universitat Autonoma de Barcelona, Bellaterra, Spain

When a low constant voltage is applied to the gate of a thin oxide MOS capacitor, the time evolution of the current measured in the soft breakdown regime exhibits a switching behavior. The fluctuations have well defined levels and are identified as on-off states of conductive spots. A conduction mechanism consistent with the experimental results is also proposed.
 
Tuesday, March 31, 2:00 p.m., Parallel Session 2
 

2A.1 Disturbed Bonding States in SiO₂ Thin-Films and Their Impact on Time-Dependent Dielectric Breakdown—J.W. McPherson and H.C. Mogul, Texas
Instruments, Dallas, TX

The temperature dependence of the field-acceleration parameter gamma depends on the disturbed molecular state(s) contributing to the breakdown reaction rate and has a direct bearing on the observed activation energy. For a single dominant disturbed-bonding state, gamma has the expected 1/T dependence while a mixing of two or more states can result in a nearly temperature independent gamma. This drives an observed activation energy that can decrease linearly with field or an observed activation energy that is field independent for two-state mixing.

2A.2 Deep-Trap SILC (Stress Induced Leakage Current) Model For Nominal and Weak Oxides—S. Kamohara, Hitachi, Ltd., Tokyo, Japan and D. Park and C. Hu, University of California-Berkeley, Berkeley, CA

In this work, we successfully develop a new quantitative ITAT-based SILC model by introducing traps with a deep energy level of around 4.0 eV to explain the two field dependencies of SILC in a consistent way. Our model suggests that for flash EPROM a 13 nm-oxide thickness is required for 1.0 fC on the floating gate to last l00 years.

2A.3 Constant Current Charge-to-Breakdown: still a Valid Tool to Study the Reliabiity of MOS Structures?—T. Nigam, R. Degraeve, G. Groeseneken, M. Heyns, and H.E. Maes, IMEC, Leuven, Belgium

It is demonstrated that the conventional interpretation of constant current Q_BD to evaluate the influence of process variations on the reliability of MOS-structures can lead to erroneous conclusions. For a fixed thickness, the comparison of Q_BD-distributions of all processes that affect the breakdown statistics becomes even meaningless. For ultra-thin oxides, the impact of different processing conditions requires constant gate voltage instead of constant current density Q_BD-tests.

2A.4 Improvement of Gate Dielectric Reliability for P⁺ Poly MOS Devices Using A Remote PECVD Top Nitride Deposition on Thin Gate Oxides—Y. Wu and G. Lucovsky, North Carolina State University, Raleigh, NC and H. Massoud, Duke University, Durham, NC

Suppression of boron penetration from a p⁺ poly-Si gate electrode by nitrogen atom incorporation at the Si/SiO₂ interface degrades gate dielectric reliability. In contrast deposition of an ultra-thin nitride layer (< 1 nm) on top of an oxide dielectric is an effective boron diffusion barrier and improves reliability as well.

2A.5 Trap Assisted Tunneling as a Mechanism of Degradaton and Noise in 2-5 nm Oxides—G.B. Alers, B.E. Weir, M. A. Alam, G.L. Timp, and T. Sorch, Lucent Technologies, Murray Hill, NJ

The mechanism of stress induced leakage current and dielectric breakdown is examined through l/f noise in the tunneling current of 2-5 nm oxides. Before breakdown occurs, we find a linear relationship between low frequency 1/f noise and the increased current due to stress and both phenomena can be described by a model of trap assisted tunneling. We also develop a new wafer-level noise test for the increase in noise at soft and hard breakdown of an oxide. We use the statistics of the post-breakdown noise levels to understand the origin in terms of a local current shunt in the oxide.

2A.6 A New Algorithm for Transforming Exponential Current Ramp Breakdown Distributions into Constant Current TDDB Space and the implications for gate oxide q_BD measurement methods—N.A. Dumin, Texas Instruments, Dallas, TX

A new, simple algorithm is proposed for transforming gate oxide breakdown distributions obtained with the exponential current ramp into constant current TDDB space. This algorithm is shown to work accurately for oxides ranging from 8 nm to 4.5 nm over several orders of magnitude of stress current density (for the constant current stress) and delay time (for the exponential ramp).

2A.7 The Correlation of Highly Accelerated Q_BD Tests to TDDB Life Tests for Ultra-Thin Gate Oxides—Y. Chen, Univ. of Maryland, College Park, MD, J.S. Suehle, NIST, Gaithersburg, MD, B. Shen and J.B. Bernstein, Univ. of Maryland, College Park, MD, C.R. Messick, Fairchild Semiconductor, W. Jordan, UT, and P. Chaparala, National Semiconductor, Santa Clara, CA

A new model and technique are presented that provide an efficient and robust method to extract long-term TDDB acceleration parameters from highly accelerated Q_BD tests. It is demonstrated that regardless of  oxide thickness, the extracted acceleration parameters are identical to those obtained from long-term TDDB tests.

2B.1 Early Variations Of The Base Current In In/C-DOPED GaInP/GaAs HBT's—M. Borgarino, R. Plana*, S. Delage**, H. Blanck**, F. Fantini, and J. Graffeuil*, Universita' di Parma, Parma, Italy                                             
                                          *CNRS, Toulouse, France
                                         **Thomson LCR, Orsay, France

This paper reports on the variation of base current in In/C-doped GaInP/GaAs HBTs under various electrical burn-in stress conditions. Measurements of both DC device characteristics and low frequency noise spectra were conducted. Results show that the increase in current gain during burn-in is due to a reduction of the extrinsic base surface recombination.

2B.2 Degradation of InGaAs/InP Heterojunction Bipolar Transistors under high energy electron irradiation—A. Bandyopadhyay, S. Subramanian, Oregon State University, Corvallis, OR, S. Chandrasekhar, Lucent Technologies, Holmdel, NJ, and S.M. Goodnick, Arizona State University, Tempe, AZ

The effect of high energy electron radiation on InGaAs/InP single heterojunction bipolar transistors has been studied. A decrease in DC current gain of 10 to 40 % and an increase in collector saturation voltage are observed for a dose of 5.4 ´ 10¹⁵ electrons/cm².

2B.3 (withdrawn)

2B.4 Dislocation Dynamics in Heterojunction Bipolar Transistor Under Current Induced Thermal Stress—C.-T. Tsai and L.L. Liou, Wright Laboratory, Wright-Patterson AFB, OH

The dislocations generated in heterojunction bipolar transistors under electrical bias was studied. A modified dislocation model was developed and employed to calculate the distribution of dislocation densities versus time. It was found that the initial rate of change and the stationary dislocation density is strongly dependent on the current density.

2B.5 A Novel, High Resolution Non-Contact Channel Temperature Measurement Technique—Q. Kim and S.A. Kayali, Jet Propulsion Laboratory, Pasadena CA

A technique based on infrared emission spectroscopy has been found to be useful for high spatial resolution, non-contact measurement of the temperature of a hot spot in the gate channel of a GaAs metal/semiconductor field effect transistor. The technique was demonstrated on a powered and un-powered GaAs device, attaining a spatial resolution of 0.5 µm.

2B.6 REDR-Based Kinetics for Line Defects Leading to Sudden Failures in 980 nm SL SQW InGaAs Laser Diodes—A. Bonfiglio, M.B. Casu, M. Vanzi, University of Cagliari, Cagliari, Italy, F. Magistrali, M. Maini, G. Salmini, Pirelli Cavi S.p.A., Milano, Italy

Recombination-Enhanced-Defect-Reaction is called to explain sudden failures in pump laser diodes. Previous reports indicate the motion of defects from outside the active layer. Here the kinetics of that phenomenon is accounted for, explaining the sudden failure occurrence with the REDR-specific exponentially increasing speed of the defect towards the active layer.

2B.7 A Novel Reliability Projection Model of Semiconductor Laser Diodes by Correlating Thermal Characteristics with Long-Term Degradation—N. Hwang, J.-T. Moon, M.-K. Song, and K.-E. Pyun, ETRI, Taejon, Korea

A novel reliability projection model of semiconductor laser diodes (LD) is presented, By correlating initial thermal characteristics and long-term degradation, a relationship between LD degradation and ambient temperature has been investigated. The proposed model is found to be efficient for the reliability projection of LDs, which requires a thermal characterization only at t = 0.

2B.8 Degradation of Single-Quantum Well InGaN Light Emitting Diodes Under High Electrical Stress—D.L. Barton, Sandia National Laboratories, Albuquerque, NM and M. Osinski, P. Perlin, P.G. Eliseev, and J. Lee, University of New Mexico, Albuquerque NM

We performed a degradation study on single-quantum well AlGaN/InGaN/GaN light-emitting diodes (LEDs) subjecting them to high current, short duty cycle pulses with amplitudes between 1 A and 7 A. Analysis showed that for currents less than 6 A, the lifetime is limited by the package while for larger currents, the metal contacts are damaged.

Tuesday March 31, 6:00 _ 6:50 p.m., South Entrance_Reno Hilton
BUSES TO MUSEUM

Tuesday March 31, 6:30 _ 9:30 p.m.
SYMPOSIUM RECEPTION—NATIONAL AUTOMOBILE MUSEUM

Wednesday, April 1, 8:15 a.m., Parallel Session 3

3A.1 (invited) A Reliability Study of titanium Silicide Lines Using Micro-Raman Spectroscopy and Emission Microscopy—I. DeWolf, D.J. Howard, M. Rasras, A. Lauwers, K. Maex, G. Groesenken, and H.E. Maes, IMEC, Leuven, Belgium

Micro-Raman spectroscopy and emission microscopy are used to study the crystallographic phase of 0.25 µm wide TiSi₂ lines. Emission microscopy allows very fast, simple, non-destructive mapping of the local phase of TiSi₂. A direct correlation is seen between the resistance variation of these lines and the local occurrence of the high resistance C49 phase of TiSi₂ in the lines.

3A.2 BaCkside Localization of Open and Shorted IC Interconnections—E.I. Cole Jr., P. Tangyunyong, and D.L. Barton, Sandia National Laboratories, Albuquerque, NM

A new failure analysis technique has been developed for rapid, backside imaging of open and shorted interconnections. This imaging mode takes advantage of the interactions between IC defects and an IR laser (l = 1.3 µm). The method utilized the Seebeck Effect to localize opens and Thermally-Induced Voltage Alteration (TIVA) to detect shorts.

3A.3 Dynamics of Backside Wafer Level Microprobing—D.T. Hurley, Hypervision, Fremont, CA

The relationship between IR transmission and the substrate silicon doping level is measured. Chip thinning procedures are discussed and methods used to compensate for the mechanical deformation of the wafer. Plots of wafer deflection under load are explained. The use of mechanical reinforcement and ultra low force probe cards in relationship to backside thinned samples is explained.

3A.4 A New Failure Mechanism by Corrosion of Tungsten in a Tungsten Plug Process—S. Bothra, H. Sur, and V. Liang, VLSI Technology, San Jose, CA

The Tungsten-filled plug process is commonly used in sub-half micron CMOS process technologies. In the evaluation of vias which are not fully covered by the overlying interconnect lines, we have observed a new failure mechanism resulting in completely unfilled vias due to electrochemical corrosion accelerated by a positive charge on specific structures.

3A.5 Cross-sectional Atomic Force Microscopy of Focused Ion BeaM Milled DeviceS—J.L. Ebel, C. Bozada, T.E. Schlesinger*, C. Cerny, G. DeSalvo, R. Dettmer, J. Gillespie, T. Jenkins, K. Nakano, C. Pettiford, T. Quach, J. Sewell,, G. Via, and R. Welch, Wright Laboratory, Wright-Patterson AFB, OH   *Carnegie Mellon University, Pittsburgh PA

Sample preparation and measurement techniques are presented for cross-sectional atomic force microscopy (AFM) of focused ion beam milled devices. AFM offers higher resolution than Scanning Electron Microscopy, and avoids the difficult sample preparation requirements of transmission electron microscopy. Application to GaAs heterojunction bipolar transistor reliability studies is discussed.

3A.6 Nanoscale Electrical Characterization of Thin Oxides with Conducting Atomic Force Microscopy—A. Olbrich, B. Ebersberger, and C. Boit, Siemens AG, Munich, Germany

Atomic Force Microscopy equipped with a conductive tip is used for Fowler-Nordheim (FN) current measurements on various thin oxides. Simultaneously with the oxide topography, local oxide thinning and weak spots are detected quantitatively on a nanometer scale length in two dimensions. The microscopic electrical behavior follows the macroscopic I-V curves in excellent agreement making the method suitable for correlations to reliability results.

3A.7 High-Resolution Current and Temperature Mapping of Electronic Devices Using Scanning Joule Expansion Microscopy—J. Varesi, M. Igeta, S. Muenster, and A. Majumdar, Univ. of California, Berkeley, CA

A new technique - scanning Joule expansion microscopy - has been developed to measure the current and temperature distributions of electronic devices and interconnects with 0.01 µm spatial resolution and 20 kHz - 1 GHz frequency bandwidth using only an atomic force microscope, and without requiring specialized sensing probes.

3B.1 Key Issues in Assessing Circuit-Level Hot-Carrier Reliability—W. Jiang, J. Chung, MIT, Cambridge, MA and T.E. Kopley, W. Li, and P.J. Marcoux, Hewlett-Packard Company, Palo Alto, CA and C. Dai, Intel Corp., Santa Clara, CA

The major factors that cumulatively determine circuit-level hot-carrier reliability are defined and characterized. The inherent inverse relationship between lifetime-underestimation/criteria- overspecification (LUCO) and the amount of known device/circuit information are explored. LUCO is shown to depend strongly on the particular worst-case approximations used.

3B.2 Effects of Advanced Processes on Hot Carrier Reliability—S. Aur, T. Grider, V. McNeil, T. Holloway, and R. Eklund, Texas Instruments, Dallas, TX

This paper studies the effects of remote plasma nitrided oxidation (RPNO), deuterium anneal, and pocket implant on hot-carrier reliability. It is found that RPNO can improve the hot-carrier reliability while an unoptimized pocket implant can degrade reliability. Under proper conditions, a deuterium anneal can improve the hot-carrier reliability, even when nitride sidewalls are present.

3B.3 Hot-Carrier Degradation Mechanism and Promising Device Design of n-MOSFETs with Nitride Sidewall Spacer—Y. Sambonsugi and T. Sugii, Fujitsu Laboratories Ltd., Atsugi, Japan

The hot-carrier reliability of n-MOSFETs with nitride sidewalls was investigated. A unique stress bias dependence of hot-carrier degradation was found, which suggests a susceptibility to hot-carrier degradation and makes lifetime estimation inconclusive. Hot-carrier reliability in nitride sidewall devices was improved by shifting the location of the hot-carrier injection.

3B.4 Effects of Halo Inplant on Hot Carrier Reliability of Sub-Quarter Micron MOSFETs—A. Das, H. De, V. Misra, S. Venkatesan, S. Veeraraghavan, and M. Foisy, Motorola, Austin, TX

Halo implants increase electric fields at the drain/channel junction. Deeper and larger tilt angle implanted halos were found to increase electric fields, and in some cases hot-carrier degradation. When device performance merits are identical, a shallower halo with larger tilt was found to have less degradation than a comparable deeper halo with lower tilt.

3B.5 Channel Coupling Imposed Tradeoffs Between Hot-Carrier Degradation and Single Transistor Latch-up in FD SOI MOSFETs—F.L. Duan, and D.E. Ioannou, George Mason University, Fairfax, VA, H.L. Hughes, Naval Research Laboratory, Washington, DC, and S.T. Liu, Honeywell SSEC, Plymouth, MN

Channel coupling in SOI MOSFETs presents a trade-off between hot-carrier reliability and latch-up. Stronger coupling lessens the impact ionization and the resulting hot-carrier degradation. However, this effect accelerates the triggering of the parasitic bipolar action, leading to latch-up voltage reduction.

3B.6 Comparison of hot-carrier effects in deep submicron n- and p-channel partially- and fully-depleted Unibond and SIMOX MOSFETs—S.H. Renn, C. Raynaud*, J.L. Pelloie*, and F. Balestra, LPCS/ENSERG, Grenoble, France    *LETI-CEA (DMEL/CENG), Grenoble, France

Reliability issues of SOI technologies are studied including; i) comparison of hot-carrier effects in SIMOX and Unibond MOSFET's, ii) evaluation of the hot-carrier immunity of fully and partially depleted devices,
iii) analysis of the degradation in n-channel and p-channel transistors and iv) investigation of the aging/recovering mechanisms.

3B.7 Voltage Scaling and Temperature Effects on Drain Leakage Current Degradation in a Hot Carrier Stressed n-MOSFET—T. Wang, C.F. Hsu, L.P. Chiang, N.K. Zous, and C.Y. Chang, National Chiao-Tung University, Hsin-Chu, Taiwan, R.O.C. and T.S. Chao, National Nano Devices Lab., Hsin-Chu, Taiwan, R.O.C.

Various drain leakage current mechanisms in a hot-carrier stressed n-MOSFET are modeled and characterized. The dependence of drain leakage current on supply voltage and temperature are evaluated. Band-to-band tunneling is a dominant drain leakage mechanism at larger supply voltage, while interface trap induced leakage appears to be a major drain leakage current component at a scaled supply voltage.

Wednesday, April 1, 2:00 p.m., Parallel Session 4

4A.1 Method for Equivalent Acceleration of JEDEC/IPC Moisture Sensitivity Levels—R.L. Shook and B.T. Vaccaro, Lucent Technologies, Allentown, PA

A method of equivalent acceleration of JEDEC/IPC moisture sensitivity Levels 3-5 and a new one month equivalent test are presented. This approach provides a means to achieve cycle time reduction during moisture/reflow testing. Reflow experiments on several package types confirm by acoustic inspection that damage responses are equivalent between the new test procedure and the current moisture levels.

4A.2 Critical Parameters for Reliable Surface Mounting of High Pincount Packages—B.L. Euzent, B. Kawanami, and S. Lau, Altera Corporation, San Jose, CA

This paper examines the moisture/reflow failure mechanisms associated with large die (45 mm² to 300 mm²) in plastic quad flatpacks (PQFPs) and thermally enhanced PQFPs with more than 200 pins. The degradation in performance with increased reflow soldering temperature and absorbed moisture is characterized, and techniques to improve performance are discussed.

4A.3 Elimination of Bond-pad Damage Through Structural Reinforcement of Intermetal Dielectrics—M. Saran, R. Cox, C. Martin, G. Ryan, T. Kudoh*, M. Kanasugi*, J. Hortaleza, M. Ibnabdeljalil, and M. Murtuza, Texas Instruments, Dallas, TX  *Texas Instruments, Hayami-Gun Olta, Japan

Bond-pad damage (dielectric fractures and metallization delaminations) during Au ball-bonding was linked to the presence of hydrogen silsesquioxane (HSQ) planarizing layers in the dielectric stacks. The damage results from exposure of weaker HSQ layers to bonding forces, enhanced by the use of ultrasonic energy. Damage is eliminated by inserting metal grid patterns at previous metal levels under the bond-pads.

4A.4 The Evolution of Hydrogen from Plastic Molding Compound and Its Effect on the Yield & Reliability of Ferroelectric Memories—E.M. Philofsky, Ramtron International, Colorado Sprgs., CO and C.R. Ostrander and S.J. Hartman, Trace Analytical, Inc., Menlo Park, CA

Hydrogen evolution was measured down to the ppb level for three different plastic molding compounds. Ferroelectric memory devices assembled using the three different molding compounds were tested for yield and retention loss. Reliability test results are found to correlate to the hydrogen evolution data. A model is presented to explain the results.

4A.5 In-Situ Monitoring of Bond Degradation in Power ICs Under High Current Stress—B. Krabbenborg, Philips Semiconductors, Nijmegen, The Netherlands

In this paper 4-point electrical measurements are presented for Au-Al intermetallic degradation developed between Au-balls and Al bondpads during high current stressing. The failure mechanism is explained and a comparison with low-current lifetime is given resulting in high current bondpad design rules.

4A.6 Prediction of Thermal Resistance Degradation During Thermal Cycling—J. Naderman, F.W. Ragay, A. van Eck, and J. van de Water, Philips Semiconductors, Nijmegen, The Netherlands

In this paper several analysis techniques are successfully used to predict thermal resistance degradation due to alloy die-attach aging of high power SO-packages. The Coffin-Manson formula is used to calculate the acceleration factor for the failure mechanism of solder alloy die attach cracking resulting in a 20% Rthj-c increase.

4A.7 Influences of Fan-in/Fan-out Structure and Underfill Fillet on TCT Reliability of Flip Chip BGA—H. Shimoe, T. Iijima, T. Iiyama, K. Oyama, H. Taguchi, and Y. Hiruta, Toshiba Corporation, Yokohama, Japan

Reliability of a large memory flip chip BGA was investigated by temperature cycling (TCT). It was found that TCT reliability of the fan-out structure was higher than that of the fan-in structure. FEA shows large stresses develop on the die at the substrate edge in the fan-in structure, while it is lower for the Fan-out structure.

4A.8 CSP Solder Joint Reliability and Modeling—M. Amagai, Texas Instruments, Oita-pref, Japan

A comprehensive experimental and numerical study of the solder joint reliability for chip scale packages (CSP) are presented. The reliability of solder joints were assessed through accelerated lifetime testing with rate-dependent deformation history investigated using viscoplastic analysis. The effect of various component parameters on the solder joint reliability was predicted using a Weibull cumulative distribution analysis.

4B.1 (invited) Latchup in CMOS Technology—
M.J. Hargrove, S.H. Voldman, R. Gauthier, J. Brown, K. Duncan,
and W. Craig, IBM Microelectronics Div., Hopewell Junction, VT

This paper is a review of the latchup phenomena in past and present CMOS technologies. Both static and transient characterization techniques are described, as well as process related solutions and layout groundrule constraints. Technology scaling implications are discussed in the context of latchup holding voltage/current & minimum N⁺/P⁺ spacing.

4B.2 A Study of ESD-Induced Latent Damage in CMOS Integrated Circuits—Y. Huh, M.G. Lee*, J.S. Lee, H.C. Jung*, T. Li, D.-H. Song*, Y.J. Lee*, J.M. Hwang*, Y.K. Sung**, and S.M. Kang, University of Illinois, Urbana-Champaign, Urbana, IL  *LG Semicon Co., Ltd., Cheongju, Korea  ** Korea University, Seoul, Korea

An investigation of package level ESD-induced latent damage in MOS transistors as well as a 64 Mbyte DRAM chip is presented. Latent damage is demonstrated by increased device and circuit parameter shifts after low-level ESD pre-stress conditioning. A relationship between latent damage effects on the transistor level and on the VLSI circuit level is observed.

4B.3 High Current Effects in Silicide Films for
Sub-0.25 µm VLSI Technologies—K. Bannerjee, A. Amerasekera*, J.A. Kittl*, and C. Hu, Univ. of California, Berkeley, CA *Texas Instruments, Dallas, TX

Behavior of thin TiSi₂ and CoSi₂ films have been characterized under high current conditions. The high current effects have been shown to cause thermal degradation in these thin silicon films leading to a transformation to poly-Si film in these regions that can significantly impact advanced circuit performance. The critical current for such degradation is shown to be strongly dependant on the surface areas of the films in contact with Si and the pulse width. Further, it has been shown that CoSi₂ films may be more susceptible to degradation under high current stress conditions.

4B.4 High-Current Transmission-Line Pulse Characterization of Aluminum and Copper Interconnects for Advanced CMOS Semiconductor Technologies—S.H. Voldman, R. Gauthier, D. Reinhart and K. Morrisseau, IBM Microelectronics, Essex Junction, VT

The critical current density-to-failure J_crit, of copper (Cu)-based wire and via interconnects as a function of pulse width is reported for the first time. The transmission line pulse testing technique for thermal impedance extraction and Jcrit evaluation, as shown by Banerjee et al, is applied to copper interconnects. The extraction methodology is extended by identifying Joule heating and electromigration-induced resistance shifts.

4B.5 Antenna Protection Strategy for ultra-thin gate MOSFETs—S. Krishnan and A. Amerasekera, Texas Instruments, Dallas, TX

We compare the efficacy of drain-well diodes, gated diodes, lateral BJT and SCR antenna protection under positive as well as negative plasma damage. Our results indicate that a nominal drain/substrate p-n junction (0.49 µm²) is capable of device protection for antenna up to 200 kµm, and can be extended down to 21 Å devices. We have shown that under severe charging, antenna protection through a single contact diode can result in diode failure. We also present several novel protection schemes.

4B.6 Reduction of Plasma-Induced Gate Oxide Damage Using Low-Energy Large-Mass Ion Bombardment in Gate-Metal Sputtering Deposition—T. Ushiki, M.C. Yu, K. Kawai, T. Shinohara, K. Ino, and M. Morita, and T. Ohmi, Tohoku University, Sendai, Japan

The effects of ion species in sputtering deposition process on gate oxide reliability have been experimentally investigated. The use of Xe plasma instead of Ar plasma in tantulum film sputtering deposition for gate electrode formation makes it possible to improve the gate oxide reliability of MOS capacitors. The Xe process produces oxides with 1.5X higher breakdown fields and 5X higher 50%-Q_BD.

4B.7 Characterization of Plasma Charging Damage in Ultrathin Gate Oxides—H.-C. Lin, C.-C. Chen*, M.F. Wang*, S.-K. Hsien**, C.-H. Chien*, T.-Y. Huang*, C.Y. Chang*, and T.-S. Chao, National Nano Device Laboratories, Taiwan, R.O.C.   *National Chiao-Tung University, Taiwan, R.O.C   **National Tsing-Hua University, Taiwan, R.O.C

The impact of plasma charging damage on oxide scaling is investigated. It is shown that, as the oxide is scaled below 3 nm, the charging damage will depend on the stress polarity, plasma uniformity, and process temperature. Among them, it is seen that the process temperature is an extremely important factor since the associated acceleration effect is very significant.

Wednesday, April 1, 7:00 _ 8:00 p.m., Grand Ballroom Foyer
BANQUET RECEPTION

Wednesday, April 1, 8:00 p.m., Tahoe Room
AWARDS BANQUET

Thursday, April 2, 8:15 a.m., Session 5, Reno Ballroom 

5.1 Stress-Induced Voiding Failure in Stacked Tungsten Via Structure—S. Domae, H. Masuda, K. Tateiwa, Y. Kato, and M. Fujimoto, Matsushita Electronics Corporation, Kyoto, Japan

The stress-induced voiding failure in a stacked tungsten via structure was investigated. There was a correlation between void location and calculated stress distribution. The failure frequency increases with plug depth, and is believed to be caused by the increased tendency to form high-angle misoriented grains above the plugs with increased plug depth. Voiding was also found to be controlled by the amount of Al₂O₃ formed on the metal sidewall surface.

5.2 Statistics of Microstructure for Via Metallization and Implication on Electromigration Reliability—H. Toyoda, P.-H. Wang, and P.S. Ho, University of Texas, Austin, TX, and M. Gall and H. Kawasaki, Motorola, Austin, TX

Electromigration damage in 0.6 µm AlCu via/line structures was found to be dominated by void formation at grain boundaries near vias. The orientation of individual grains near vias was measured using electron backscatter diffraction. The local grain misalignment is correlated with void formation during electromigration.

5.3 Ti Layer Thickness Dependence on Electromigration Performance of Ti/AlCu Metallization—M. Hosaka, T. Kouno, Y. Hayakawa, H. Niwa, and M. Yamada, Fujitsu Ltd., Kanagawa, Japan

Electromigration lifetime tests on TiN/Ti/AlCu/TiN/Ti stacked structures having various upper Ti thickness have been carried out on two-level interconnect structures with W-plug via chains. A high electromigration lifetime was obtained with thin Ti, compared to thick Ti. Data is presented to support a new model that suggests this is caused by Al flux divergence in the discontinuous Ti₃Al that forms when the upper Ti thickness is small.

5.4 Effect of H₂O Partial Pressure and Temperature During Ti Sputtering on Texture and Electromigration in AlSiCu/Ti/TiN/Ti Metallization—T. Yoshida, S. Hashimoto, Y. Mitsushima, T. Ohwaki, and Y. Taga, Toyota R&D Labs., Inc., Aichi-ken, Japan

The (002) preferred texture of Ti underlying films sputter-deposited on silicate glass substrates was drastically improved by controlling the H₂0 partial pressure during the film deposition at 350 °C. AlSiCu/Ti/TiN/Ti interconnects with the improved Ti film showed a strong Al(111) texture and larger EM lifetimes.

5.5 The Electromigration performance of Cu Damascene Interconnects with Crystallographic Texture Control—K. Abe, Y. Harada, and H. Onoda, Oki Electric Industry Co., Ltd., Tokyo, Japan

Improved EM performance for Cu Damascene interconnect is investigated, by studying the dependence of Cu texture with various underlayer processing. The Cu(111) orientation is enhanced on TiN film having a strong Ti(111) orientation. Damascene Cu interconnects with stronger (111) orientation have longer EM MTTF. The effect of underlayer texture on Cu film orientation becomes smaller as line width decreases.

5.6 Effect of VLSI Interconnect Layout on Electromigration Performance—E.M. Atakov, T.S. Sriram, D. Dunnell, and S. Pizzanello, Digital Equipment Corporation, Hudson, MA

The EM reliability of Ti/Al(Cu)/TiN leads for multiple-via Kelvin structures, the impact of current direction on the failure statistics, and the threshold effect in via-terminated links of varying lengths was characterized. The implications for interconnect design rules and metal stack optimization are discussed.

5.7 Full-Chip interconnect Reliability Analysis—S. Rochel, G. Steele, J. Lloyd*, and D. Overhauser, Simplex Solutions, Inc., Sunnyvale, CA  *Lloyd Technology Associates, Inc., Stowe, MA

Reliability analysis has not been promoted to the realm of full-chip because techniques to extract, manage, and process full-chip data have not been previously available. This paper introduces techniques that have been developed to permit both full-chip power grid and signal net electromigration and Joule heating analysis. Results of this analysis provide feedback to the circuit designer to permit design modification.

Thursday, April 2, 2:00 p.m., Session 6, Reno Ballroom 

6.1 A Comparative Study of Leakage Mechanism of Co and Ni Salicide Processes—K. Goto, J. Watanabe, T. Sukegawa*, A. Fushida*, M. Sakuma*, and T. Sugii, Fujitsu Laboratories Ltd., Atsugi, Japan *Fujitsu Ltd., Kawasaki, Japan

Using a light emission method, a direct observation was made of the leakage points on Co and Ni salicided junctions. A stress-induced spike growth model is proposed for Co salicide taking into account the Co₂Si/CoSi stress and for Ni salicide the LOCOS edge stress. Considering this model, a Co salicide process is developed using a Ge pre-amorphization step that can completely solve the spike leakage.

6.2 Impact of Screening of Latent Defects at Electrical Test on the Yield-Reliability Relation and Application to Burn-In Elimination—J.A. van der Pol, E. Ooms, A. van `t Hof, and F. Kuper, Philips Semiconductors, Nijmegen, The Netherlands

Based on data of millions of sold devices, the effect of screening of latent defects at electrical test on product reliability has been investigated. The results are combined with the experimentally determined failure rate time evolution leading to a model that allows one to quantitatively determine under which conditions burn-in screen at electrical test can be eliminated.

6.3 Extended Data Retention Process Technology for Highly Reliable Multi-Level FLASH EEPROMs of More than 10⁶ W/E Cycles—F. Arai, T. Maruyama, and R. Shirota, Toshiba Corporation, Yokohama, Japan

Using 16 Mbit flash memories, the relation between data retentivity and the density of silicon surface micro-defects just before the tunnel oxidation process is clarified. It is shown that by reducing the surface micro-defect density to less than 1.2 ´ 10²⁰/cm³, data retention life time of multi-level flash memories can be extended more than 10 times.

6.4 Hot-Electron Degradation and Unclamped Inductive Switching in Sub-micron 60V Lateral DMOS—M.S. Shekar, M. Cornell, M.-Y. Lio, M. Darwish, and R.K. Williams, Siliconix Inc., Santa Clara, CA

Trade-offs are examined between HE degradation and UIS ruggedness for 60V lateral N-LDMOS devices integrated in a 0.8 micron BCD (Bi-CMOS-DMOS) twin-well sub-micron VLSI CMOS process. MEDICI and SUPREM-IV simulation is used to study hot-electron and UIS performance associated with As and P-graded N-LDMOS devices. For the first time, the time-dependence of of N and P-channel L-DMOS parameter degradation is presented.

6.5 The Experimental Investigation on Single Event Upset in SRAM Induced by the Reaction of Thermal Neutrons and BPSG Film—Y. Arita, H. Kuriyama, and Y. Haraguchi, Mitsubishi Electric Corporation, Hyogo, Japan and I. Ogawa and T. Kishimoto, Osaka University, Osaka, Japan

We experimentally investigated the effect of the BPSG layer on neutron induced SEU in static random access memory. We confirmed that the thermal neutron reacted with ¹⁰B and induced SEU. The acceleration test using californium (²⁵²Cf) was a useful and convenient method to evaluate neutron induced SEU.