The 1998 IRPS Tutorials program offers a unique opportunity for those who are new to the field of reliability physics to gain some focused learning in one day on difficult topics from experts in their field. It also provides an avenue for experienced engineers to refresh their thinking and to exchange technical viewpoints with other experts. Furthermore, the tutorial provides an economical alternative to bringing experts to your plant location.
In order to present the most popular subject matter, feedback from last year's attendees helped determine this years topics. Where appropriate the presenter will spend some time developing the fundamental aspects in each topic so that new and cross disciplined engineers can easily accomplish their goals of learning the subject.
You are encouraged to register early and indicate your tutorial selection on your advanced registration form so that appropriate room assignments can be made. The tutorial fee entitles each attendees to enroll in a full day of courses. The tutorial registration fee is $210 with advanced registration and $250 with registration at the door. Each attendee registered for the tutorial will receive a complete copy of the 1998 IRPS Tutorial Notes at the Symposium registration desk.
Monday March 30, 1997
| 8 to 9:30 | 10 to 11:30 | 2 to 5 p.m. | ||
| Carson 1/2 | Topic 1 | Topic 5 | Topic 10 | |
| Tahoe Ballroom | Topic 2 | Topic 7 | ||
| Reno Ballroom | Topic 3 | Topic 6 | ||
| Carson 3 | Topic 4 | Topic 9 | ||
| Carson 4 | Topic 8 | |||
The choice of design path for scaling device dimensions depends in large part upon the models used to project dielectric and hot carrier reliability. The available data on devices with 0.25 micron lithography and below and dielectric thickness of 40 Å and below is rapidly increasing. Key device reliability papers of the last year or so will be reviewed briefly and placed in the context of current understanding.
Topic 2. SCANNING PROBE MICROSCOPY FOR IC ANALYSIS— Y. Strausser, Digital Instruments, Santa Barbara, CA, A. Majumdar, University of California, Berkeley, CA, C. Williams, University of Utah, Salt Lake City, UT, and W. Mertin, University of Duisburg, Duisburg, Germany (8:00 a.m. - 11:30 a.m., Tahoe Ballroom)
While the original applications of scanning probe microscopy (SPM) centered on nanometer-scale surface science, a variety of applications suitable for the study of semiconductor properties and IC operation have been developed in the last few years. This tutorial will begin by reviewing the basics of SPM operation and will then explore several advanced applications in the field which are of great current interest as methods of characterizing integrated circuits with submicron resolution. The use of a thermocouple as an AFM tip allows submicron resolution of temperature profiles which in turn enables determination of local heating in devices or metallization. Scanning capacitance microscopy enables the determinations of two dimensional profiles with nanometer scale spatial resolution. Similarly SPM-based voltage contrast and current contrast imaging enable characterization of potential and current distributions in functioning ICs.
Topic 3. NITRIDED OXIDES IN CMOS TECHNOLOGY: PAST, PRESENT, AND FUTURE—B. Maiti, Motorola APRDL, Austin, TX (8:00 a.m. - 9:30 a.m., Reno Ballroom)
Scaling of CMOS technology to deep submicron channel lengths poses new challenges out of which scaling of gate dielectrics is very important. The role of silicon oxynitride dielectrics has become increasingly important in meeting these challenges in comparison to conventional silicon dioxide. This tutorial will present an overview of the evolution and understanding of the current state of the art of silicon oxynitrides for gate and tunnel dielectrics. Discussion will include 1) process options and implications, device performance/reliability trade-offs and optimisation, 3) process control, manufacturability and extendibility to present and future CMOS technology.
Topic 4. SURVEY OF MEMS PROCESSES AND FAILURE MECHANISMS—W. Tang, Jet Propulsion Laboratory, Pasadena, CA; C. Muhlstein, Failure Analysis Associates, Framingham, MA, and S. Brown, Failure Analysis Associates, Framingham, MA (8:00 a.m. - 11:30 a.m., Carson 3)
Many new Micro Electromechanical (MEMs) devices are being introduced. Fabrication of MEMs may be accomplished through bulk processes such as anisotropic wet etching of silicon, gas phase etching of silicon, etch stop techniques and wafer bonding. In addition surface micromachining techniques such as those using polysilicon deposition, sacrificial materials and sacrificial etching will be surveyed. Failure mechanisms of MEMs will also be reviewed. Because of the importance of mechanical failure mechanisms, fracture mechanics and its application to silicon and integrated circuit technologies will be discussed in some detail.
Topic 5. RECENT ADVANCES IN MULTILEVEL METALLIZATION RELIABILITY—M. Small, Martin Small Associates, Albuquerque, NM (10:00 a.m. - 11:30 a.m., Carson 1/2)
Approximately 150 papers have been surveyed and almost half of these are referenced in this survey of recent publications related to the reliability of interconnect systems for integrated circuits. The survey begins by covering advanced interconnect systems i.e. copper interconnects and low k dielectrics. The majority of the time will be spent covering Al(Cu) based systems with presently used dielectrics, mostly silicon dioxide.
Topic 6. DIELECTRIC RELIABILITY PHYSICS USING SPM—R. Ludeke and H. Wen, IBM T.J Watson Research Center, Yorktown Heights, NY (10:00 a.m. - 11:30 a.m., Reno Ballroom)
The tip of a scanning tunnelling microscope was used to inject hot electrons across the gate and into the oxide of a metal-oxide-semicondutor structure, This method of ballistic electron emission microscopy (BEEM) allows an arbitrary choice of the energy of the injected electrons. The high current densities and choice of energy make BEEM an attractive method to study hot electron transport and breakdown phenomena in dielectrics. Changes in BEEM spectra with injected electron charge are interpreted in terms of a three stage process to breakdown: 1)electron trap creation and filling, 2) prebreakdown believed to occur through thinning of the oxide, 3) oxide punch through characterised by an injection threshold close to that of silicon.
Topic 7. AN OVERVIEW OF IC FAILURE ANALYSIS—T. Barrette, Gatefield Corp., Fremont, CA, J. Hidy, LSI Logic Inc. Fremont CA, and K. Weaver, LSI Logic Inc. (1:30 p.m.-5:00 p.m. Tahoe Ballroom)
This tutorial will provide a general introduction to failure analysis of integrated circuits. First there will be a general discussion of the goals of failure analysis, definition of failure types and a typical distribution of actual customer returns. Next the analysis of functional fails using electrical techniques, dynamic EMMI, dynamic liquid crystal, and current related tools. The method of decapping of various package types, deprocessing and cross section to expose defects will be described. Finally there will be a discussion of the evolution of the requirements for future failure analysis tools and methods.
Topic 8. THERMAL EFFECTS IN INTERCONNECTS—W. Hunter and W.-Y. Shih, Texas Instruments, Dallas, TX, and K. Banerjee, University of California, Berkeley, CA , (1:30 p.m.-5:00 p.m. Carson 4)
Thermal effects are an inseparable aspect of current conduction in interconnects, due to Joule heating caused by the current flow. Self consistent solutions for current density and their dependence on duty cycle and technology will be introduced. The scaling trends of technology which drive consideration of thermal effects and numerical and other methods for analysing circuits will be covered. In addition high current and electrostatic discharge effects in metal leads and encapsulated with silicon dioxide and low k dielectrics will be reviewed.
Topic 9. FLIP CHIP and BALL GRID ARRAY PACKAGING—R. Master, Advanced Micro Devices, Sunnyvale CA (1:30 p.m.-5:00 p.m., Carson 3)
While flip chip and ball grid array packaging allow high density area contacts, these packaging methods introduce interfacial adhesion and well known solder reliability issues. Through analysis of actual failures and the distribution of failures during thermal cycle and various moisture stressing of components design and process improvements may be realised.
Topic 10. HOT CARRIER DEGRADATION IN SUB-MICRON CMOS TECHNOLOGIES: PROBLEMS AND POSSIBLE SOLUTIONS— R. Bellens, Alcatel Telecom, Antwerp, Belgium (1:30 p.m.-5:00p.m., Carson 1/2)
The first part of this tutorial discusses the phenomenon of hot carrier degradation in MOSFETs using two methods of characterising it: I-V and charge pumping measurements. The difference between AC and DC operation is treated including methods of developing unified practical degradation models. The trend towards reduced hot carrier reliability at use conditions in spite of reduced supply voltages requires more sophisticated models during circuit design. The second part of the tutorial deals with methods of building in reliability during process and design development. Specifically transistor design and processing (e.g. deuterium annealing),and circuit design methods allow the development of reliable integrated circuits.