WORKSHOPS
Monday, March 30, 7:30 p.m. - 9:30 p.m.
Chair: Eric S. Snyder, Sandia Technologies

Twelve workshops and panels covering important topics in reliability physics are available to all symposium registrants. Moderators will discuss topics of current interest and attendees are expected to participate. Attendees are encouraged to prepare questions or bring data on related topics which they may wish to discuss. Overhead projectors will be available in the meeting rooms.

Please note that the workshops will be held on Monday evening after the tutorials. Please register for the workshop of your choice when you register at the conference. Topics and moderators are listed below. For further information on the workshop program contact Eric Snyder (phone 505-872-0011, fax...0022, email: SnyderST@aol.com).

Workshop 1. PLASMA DAMAGE
Moderators - K.P. Cheung, Lucent Technologies; N. Bui, AMD; T. Brozek, Motorola

This workshop will focus on plasma-charging damage which is a subset of plasma damage. While charging damage becomes much more serious when the gate oxide thickness is reduced to sub-100 Å, there are suggestion that when the gate oxide is 30 Å or below, charging damage would no longer be a problem. We will debate this issue in the workshop. In addition, contactless techniques for charging assessment has become popular recently, we will debate its merit in the workshop. We will also discuss damage effect on hot-carrier life-time, annealability of damage, and the type of damage that are of most concern to yield and reliability. (K. Cheung, 908-582-6483).

Workshop 2. MEETING THE FAILURE ANALYSIS CHALLENGES OF THE SEMATECH ROADMAP
Moderators - E.I. Cole, Jr., Sandia National Labs; M. Bahrami, Digital Equipment Corporation

The new SEMATECH roadmap has three target areas for FA development: Backside FA Tools, Software Fault Analysis, and Advanced Deprocessing. We will address the reasons for these needs and how attendees are planning to meet these goals. Attendees are encouraged to report on their experiences in meeting these challenges. (E. Cole, 505-844-1421)

Workshop 3. PRODUCT FUNCTIONAL RELIABILITY
Moderators - W. Ellis, IBM; J. Okamura, Toshiba; D. Douse, IBM

This workshop will discuss interactions of classical reliability engineering and electrical and physical product design. Various aspects of design techniques for manufacturability, reliability and testability at different levels of product assembly will be reviewed. (W. Ellis, 802-769-7235)

Workshop 4. ULTRATHIN OXIDE CHARACTERIZATION AND RELIABILITY
Moderators - P. Chaparala, National Semiconductor; R. Degraeve, IMEC; G. Alers, Lucent Technologies

Does soft or quasi-breakdown occur in good oxides ? or is it a signature of a poor quality oxide ? How to detect it ? Moderators will focus the group discussion on characterization techniques and metrics for reliability prediction of ultrathin (less than 5 nm) gate oxides. (P. Chaparala, 408-721-8985)

Workshop 5. RELIABILITY AND PERFORMANCE ISSUES IN ADVANCED METALLIZATION
Moderators - T. Sullivan, IBM (802-769-3053); M. Dion, Harris

Workshop 6. NEW HOT CARRIER CHALLENGES IN ADVANCED SUBMICRON CMOS DEVICES
Moderators - G. La Rosa, IBM; J. Tao, AMD

The discussion of this workshop will cover new phenomena which have been observed to contribute to the HC degradation of submicron (Leff £ 0.1 µm) CMOS devices more than direct impact ionization (secondary impact ionization, electron-electron scattering, NBTI etc.). The adequacy of the standard HC characterization methodologies as well as failure criteria to take these new effects into account will be also reviewed. (G. La Rosa, 914-892-3179)

Workshop 7. WAFER LEVEL RELIABILITY
Moderator - M. Webb, Intel

Advanced semiconductor products require determination of reliability indicators while still in wafer form. Discussion will cover development and implementation of wafer-level test techniques to build reliability into a product. We will cover current techniques being used in process development and high volume production, discuss problems and successes seen with these techniques and determine what is needed to proliferate wafer level testing. (M. Webb, 505-893-7338)

Workshop 8. MICRO-ELECTRO-MECHANICAL SYSTEMS, MICRO-NANO TECHNOLOGIES RELIABILITY
Moderator - R.A. Lawton, JPL; G. Fedder, Carnegie Mellon Univ.; D. Koester, MCNC-MUMPS; C. Muhlstein, Failure Analysis Associates

MEMS requires an interdisciplinary approach to succeed. An infrastructure to facilitate rapid feedback on reliability assessment for process improvement is being developed. This workshop will discuss this infrastructure and its opportunity to prove the utility of MEMS technology. (R. Lawton, 818-354-6167)

Workshop 9. BALL GRID ARRAY TECHNOLOGY
Moderators - V.R. Holalkere, Level One Communications; B. Sen, Sun Microsystems; L. Moresco, D. Love, Micromodule Systems; J. Joroski, ChipPAC; W. Wong, Fujitsu Microelectronics

The workshop will discuss the wide variety of applications of the emerging BGA packaging technology with special emphasis on the thermal and electrical implications on the substrate design. OMPAC and thermally enhanced BGA assemblies, materials and equipment details will be covered. BGA package reliability and rework as well as some advanced FLIP-CHIP BGAs will conclude the workshop agenda.

Workshop 10. ELECTROSTATIC DISCHARGE RELIABILITY
Moderators - C. Duvvury, Texas Instruments; L. Avery, Sarnoff; J.W. Miller, Motorola

ESD continues to be a major reliability threat as technologies advance further into the deep submicron regime and IC designs get more complex. This workshop will address the latest concerns for ESD including: 1) core damage, 2) charge trapping, 3) new technology developments, 4) building-in ESD reliability, 5) mixed voltage circuits, 6) Charged Device Model, 7) oxide reliability, 8) simulation and modeling efforts to solve ESD, and 8) any other topics of interest to the audience.

Workshop 11. NEW AND CURRENT ISSUES AND APPLICATIONS OF FOCUSED ION BEAM TECHNOLOGY
Moderator - K.S. Wills, Texas Instruments

New and current issues for FIB will be discussed in this on-going users' group. Participants should contact the moderator prior to the workshop to offer to discuss their recent work. (S. Wills, 281-274-5886)

Workshop 12. SCANNING PROBE MICROSCOPY (SPM)
Moderators - P. Tangyunyong, Sandia National Laboratories; Y. Strausser, Digital Instruments

This will be the first workshop on SPM being held at IRPS. Discussion will cover a wide range of SPM techniques and their application in IC reliability and failure analysis. (P. Tangyunyong, 505-844-3460)
 

Users Group Meeting. Scanning Laser Microscopy Users Group*
Moderator - E.I. Cole, Jr., Sandia National Laboratories

*This informal working group will meet on TUESDAY, March 31, for 1 hour, starting 15 minutes after the end of the last technical session. The purpose is to share experiences and concerns using the Scanning Laser Microscopy for microelectronics analysis. Attendees are encouraged to bring vugraph examples for presentation. (E. Cole, 505-844-1421)