Program



Keynote Speakers / Luncheon Speaker


Keynote Speakers


Keynote 1:  "Transistors and Reliability in the Innovation Era", Kaizad Mistry, Vice President and Director of Logic Technology Integration, Logic Technology Development Group, Intel Corporation

Traditional transistor scaling drive the semiconductor industry through the 1990s, but led to the era of innovation driven transistor scaling. Strained silicon, high-k plus metal gate transistors, and fin based transistors were some of the key innovations in the last several process technology generations. This presentation will explore both the transistor scaling benefits from these innovations as well as the reliability implications covering the 90nm to 14nm timeframe.

Biography: Kaizad Mistry is vice president of the Technology and Manufacturing Group, and is currently responsible for directing process development activities for Intel's 10nm logic technology. Most recently, he managed the development of Intel's 22nm logic technology, the world's first to feature 3-D Tri-Gate transistors. Previously, he managed the development of Intel's 45nm logic technology, the world's first to feature high-k plus metal gate transistors. He was the device group manager for Intel's 90nm logic technology and played a leadership role in the world's first implementation of strained silicon transistors. Prior to joining Intel in 1998, Mistry managed the device physics & reliability group for the semiconductor technology division at Digital Equipment Corp. Mistry is an IEEE fellow, has authored or co-authored more than 70 journal and conference papers and holds 20 patents. In 2006, he was General Chair of the IEEE International Electron Devices Meeting.

Keynote 2: "Hybrid Memory Cube: Achieving High Performance and High Reliability", Brent Keeth, Senior Fellow, Advanced DRAM Architectures, DRAM Solutions Group, Micron Technology, Inc.

This keynote presentation will explore the genesis, architecture and construction of the Hybrid Memory Cube. The presentation will open with a discussion on how both technical and market forces led to the creation of HMC. This will be followed by a dive into the Gen 2 HMC design—detailing the design goals for the device and how manufacturability was a priority from day one. 3D integration is pivotal technology for HMC. As such, it will be explored in the context of key enablers and ongoing challenges. Finally, the presentation will discuss how HMC encompasses a variety of RAS features to improve manufacturability and to ensure long term device reliability.

Biography: Brent Keeth is a senior fellow in and has been with Micron Technology since 1992, where he directs ultrahigh performance memory design and technology development programs including the Hybrid Memory Cube (HMC). Mr. Keeth earned BSEE (1982) and MSEE (1996) degrees from the University of Idaho and is an inventor on 257 U.S. patents and 184 foreign patents to date. He also coauthored textbooks DRAM Circuit Design—Fundamental and High-Speed Topics and DRAM Circuit Design—A Tutorial, both published by Wiley-IEEE Press in 2008 and 2001 respectively. Brent has reviewed papers for publication in the Journal of Solid-State Circuits and served numerous times on technical program committees for both the International Solid State Circuits Conference and the Symposium on VLSI Circuits.

Luncheon Talk


Luncheon Date and Time:Wednesday, April 22, from 12:15 p.m. to 2:15 p.m.

The Path to High Reliability in Consumer Electronics, Pat Tang, Director of Product Integrity, Amazon Lab126

How can high reliability be achieved in fast paced consumer electronics? With competing pressures of time to market, cost and feature set, how can reliability be effectively incorporated into the product. This talk will examine a product integrity vision based on 3 technical strategies:

1. Design for reliability through simulation tools;
2. Quantifying the cost of field failure to the overall business;
3. Development of customer-use centric standards.

The path to incorporating these strategies has been long and arduous but has ultimately led to higher reliability and customer satisfaction. Technical examples with lessons learned will be given to detail how this works in practice. This presentation also aims to open the path towards a consumer electronics reliability standard and methods to be applied to the most popular electronic products today.

Biography
Pat Tang joined Amazon in 2010 as Director of Product Integrity, responsible for the architectural integrity and product reliability of Amazon’s Kindle Fire tablets, e-readers, Fire TV and Fire Phone products. He built teams of architectural simulation and materials testing, product reliability qualification and database field analysis for warranty cost. By using cloud-based simulation to aid design, thin, lightweight and reliable products like Kindle Fire HDX 8.9 and Kindle Paperwhite were realized.

Pat was previously at Apple where he was the reliability manager responsible for the qualification of Mac products: Macbook Pro, Macbook Air, iMac, MacPro, AppleTV and the first prototypes of iPad. Here he introduced large-scale reliability waterfalls to combine different stresses to replicate field use.

With interests in Physics and design Pat has also: designed the sensor pattern in Apple’s Magic trackpad; designed and patented a semiconductor sensor for green house gases; designed power amplifier probes to perform RF measurements at wafer level; conducted theoretical and empirical research of semiconductor quantum wells for opto-electronics. Patrick holds a PhD degree in Physics from Imperial College UK and has over 30 publications.

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