2026 Tutorials
Inside Program: Conference Program l Keynote Speakers l Tutorials
Workshops l Year in Review l Highlighted Papers | Invited Speakers
New for IRPS 2026: A Tailored Tutorial Experience
Foundational Pillars (90 Minutes)
The Format: 75-minute lecture followed by a 15-minute interactive Q&A.
The Goal: These sessions provide a comprehensive, high-level overview of critical reliability topics.
Who it’s for: Attendees looking to broaden their knowledge base or enter a new sub-field with a solid theoretical and practical grounding.
Frontier Deep Dives (60 Minutes)
The Format: 45-minute intensive session followed by a 15-minute technical Q&A.
The Goal: Fast-paced, concentrated explorations of niche topics and cutting-edge research.
Who it’s for: Experienced engineers and researchers seeking in-depth analysis and the latest breakthroughs without the introductory overview.
| Time | Grand Ballroom Salon BC | Grand Ballroom Salon A | Catalina Ballroom |
|---|---|---|---|
| 22 March Sun 8:30–10:00 |
Grand Ballroom Salon BC |
Grand Ballroom Salon A |
Catalina Ballroom |
| 22 March Sun 10:30–11:30 |
Grand Ballroom Salon BC |
Grand Ballroom Salon A |
Catalina Ballroom |
| 22 March Sun 1:00–2:30 |
Grand Ballroom Salon BC |
Grand Ballroom Salon A |
Catalina Ballroom |
| 22 March Sun 3:00–4:00 |
Grand Ballroom Salon BC |
Grand Ballroom Salon A |
Catalina Ballroom |
| 22 March Sun 4:30–5:30 |
Grand Ballroom Salon BC |
Grand Ballroom Salon A |
Catalina Ballroom |
| 23 March Mon 8:30–10:00 |
Grand Ballroom Salon BC |
Grand Ballroom Salon A |
Catalina Ballroom |
| 23 March Mon 10:30–11:30 |
Grand Ballroom Salon BC |
Grand Ballroom Salon A |
Catalina Ballroom |
| 23 March Mon 1:00–2:30 |
Grand Ballroom Salon BC |
Grand Ballroom Salon A |
Catalina Ballroom |
List of Tutorials
(TUT2) 22nd March 8:30-10:00 AM PST, Grand Ballroom Salon A
A Review of Reliability in GaN Power HEMTs
Matteo Borga (IMEC)
This tutorial examines the main reliability aspects of GaN power HEMTs, focusing on key device elements such as buffer layers and gate structures. It outlines mechanisms that limit device reliability and stability, along with dynamic behavior and trapping effects, their characterization, and impact on the device performance. It will provide a concise perspective on principles essential for ensuring efficient and reliable operation in advanced GaN power electronics.
Matteo Borga is an R&D Engineer at imec, specialized in GaN power electronics with strong expertise in device physics, reliability, and advanced electrical characterization of power semiconductors. Matteo earned a Master’s degree in Electronic Engineering from the University of Padova in 2016 and completed a Ph.D. in Information Engineering at the same university in 2020. During the Ph.D., Matteo focused on reliability characterization of GaN power devices, including HEMTs and vertical MOSFETs.
Currently, Matteo’s work centers on advancing lateral HEMT device technology across a broad range of application voltages and contributing to the development of vertical GaN MOSFET devices. This involves integrating device design, physics-based modeling, and advanced electrical characterization to gain deep insights into the physical mechanisms that limit device performance and reliability, enabling improvements in both architecture and process optimization.
(TUT3) 22nd March 8:30-10:00 AM PST, Catalina Ballroom
Resistive Random Access Memory for High Density Storage and Computing Applications
Daphne Chen (Ying-Chen) (Arizona State University)
This tutorial provides an overview of resistive random-access memory (RRAM) as a next-generation memory solution, highlighting its high scalability, low power consumption, fast switching speed, and strong potential for future in-memory computing. We will explore both linear and nonlinear RRAM devices enabled by oxide thin films, microstructural modulation, and low-dimensional heterogeneous integration. Specific focuses will include the reliability challenges on 1R-only RRAM configuration, where intrinsic nonlinearity facilitates scalable, energy-efficient, high-density storage, and high-performance computing applications.
Dr. Daphne Chen received a Ph.D. in Electrical and Computer Engineering from The University of Texas at Austin in 2019. She is currently an Assistant Professor in the School of Electrical, Computer and Energy Engineering at Arizona State University. Prior to joining ASU, she was an R&D Emerging Memory Engineer in the path-finding group at Micron Technology, where she contributed to the development of next-generation memory solutions. At ASU’s Semiconductor Device Research Laboratory (SDRL), her research focuses on materials for emerging devices, physical modeling, novel computing paradigms, hardware security, and energy-efficient computational architectures—particularly focusing on back-end-of-line (BEOL) compatible integration for future electronics. She holds 3 U.S. patents, involved in 4 books, and has authored over 80 research papers published in international journals and conferences on the topics of emerging memory technologies and semiconductor devices.
(TUT4) 22nd March 10:30-11:30 AM PST, Grand Ballroom Salon BC
Reliability and Test of System-in-Package Semiconductors in the AI Era
Mehul Shroff (NXP)
Modern semiconductor products support various applications, diverse functionality, and increased performance and reliability requirements, resulting in technology scaling to ever-shrinking dimensions with novel materials, device architectures, and packaging. As a result, the industry is moving to a system-in-package approach. Comprehensive, cost-efficient testing is necessary to minimize escapes. Reliability requirements necessitate collaboration among various stakeholders. This talk will explore key considerations, including machine learning and artificial intelligence, for system-in-package reliability and test, to ensure successful products.
Mehul Shroff is a Fellow and Six Sigma Black Belt at NXP Semiconductors in Austin, TX, USA, with over 30 years of experience in the semiconductor industry. His current interests are focused on reliability tools and methodologies, design for reliability, and data science and machine learning for quality and reliability. His prior experience includes process integration and device engineering in manufacturing, technology transfer, and development, module development, yield engineering, and test vehicles and test structures. He holds graduate degrees in Chemical Engineering and Software Engineering.
(TUT5) 22nd March 10:30-11:30 AM PST, Grand Ballroom Salon A
Radiation Effects in GaN
Tania Roy (Duke University)
Dr. Tania Roy is an Associate Professor in the Department of Electrical and Computer Engineering at Duke University. Prior to joining Duke in 2023, she was a faculty at University of Central Florida from 2016 to 2022. Her current research interests lie in developing hardware for artificial intelligence applications using novel functional materials including two-dimensional materials. She works on radiation effects and reliability of GaN, and the development of materials beyond silicon, such as amorphous oxide semiconductors and 2D materials. She won the PECASE award in 2025, NSF CAREER award in 2019, UCF Luminary award in 2021. She was nominated as a “Rising Star in EECS” in 2014. She is a core organizer of premier conferences in her research area, serving as the Technical Program Chair of Device Research Conference and the Emerging Device and Compute Technology subcommittee chair of IEDM. She is also an Associate Editor of NPJ 2D Materials and Applications. Roy was a postdoctoral researcher at University of California, Berkeley and Georgia Institute of Technology. She obtained her PhD and MS degree in Electrical Engineering from Vanderbilt University.
(TUT6) 22nd March 10:30-11:30 AM PST, Catalina Ballroom
Journey with AI for Accelerating Reliability Estimation from Transistors to GDS
Hussam Amrouch (Technical University of Munich)
This tutorial will demonstrate how machine learning and deep learning techniques can significantly accelerate reliability analysis across the entire design stack—from TCAD simulations to the final GDS level of advanced chips. We will highlight how aging-induced degradations and self-heating effects can be modeled and estimated with high accuracy at the GDS level, even for highly complex designs such as full processors under workload-induced activities and advanced AI accelerator IPs.
Hussam Amoruch is Professor heading the Chair of AI Processor Design within the Technical University of Munich (TUM), Germany. He is also the head of Brain-inspired Computing at the Munich Institute of Robotics. Further, he is the head of the Semiconductor Test and Reliability department at the University of Stuttgart, Germany. He is also the Academic Director of TUM Venture for Semicondcutor. He is also Fouding Director of the Munich Advanced-Technology Center for AI Chips. He received his Ph.D. degree with the highest distinction (summa cum laude) from KIT, Germany in 2015. He has over 310 publications (including over 125 articles in many top journals) in multidisciplinary research areas covering semiconductor device physics, circuit design and computer architecture. His research interest is design for reliability, AI acceleration, emerging technologies, in-memory computing, and cryogenic circuits . His research in AI chips and reliability have been funded by the German Research Foundation, Bavarian ministry of economy, Bavarian ministry of science, Advantest Corporation, and EU.
(TUT7) 22nd March 1:00-2:30 PM PST, Grand Ballroom Salon BC
Reliability Engineering for Hyperscale Datacenters: Methods, Metrics, and Models
Lakshimi Kari & Felipe Vallini (Celestial AI)
Hyperscale datacenters are evolving rapidly with the adoption of next-generation technologies such as high TDP XPUs (GPU/AI ASICs etc), advanced electrical and optical scale-up & scale-out interconnects, direct-to-chip liquid cooling, etc. These innovations enable unprecedented performance but introduce new reliability challenges across thermal, electrical, and mechanical domains. This talk examines the methods, metrics, and models for ensuring robust reliability in this dynamic environment. Key topics include: Impact of Emerging Technologies on reliability—high-density packaging, advanced cooling, and power delivery; Failure Mechanisms and Stress Factors in modern server and interconnect hardware; Quantitative Reliability Metrics for uptime, MTBF, and component-level qualification; Accelerated Life Testing for high-performance systems; Design-for-Reliability Strategies to mitigate risks in advanced datacenter architectures
Lakshmi Kari serves as Director of Quality and Reliability at Celestial AI, for silicon photonics hardware platforms. She brings two decades of semiconductor experience spanning device physics, failure analysis, and system-level reliability. Lakshmi’s work focuses on developing scalable quality systems and advancing data-driven reliability methodologies for emerging hardware technologies.
With two decades of experience in the semiconductor industry, she spent the last twelve years at Qualcomm, where she helped scale the company’s Automotive Quality & Reliability framework and later led the Global Product/Technology Reliability organization. Before joining Qualcomm, she spent her career at ON Semiconductor, University of Maryland as Research Faculty, and Amkor Technologies. She holds an M.S. in Electrical Engineering and is an ASQ Certified Reliability Engineer.
Felipe Vallini is a Staff Reliability Engineer at Celestial AI, specialized in reliability of silicon photonics integrated circuits and co-packaged optics. Prior to Celestial AI, Felipe spent eight years at Intel as a Silicon Photonics Reliability Engineer, contributing to the reliability demonstration of heterogeneously integrated hybrid lasers and the qualification of optical transceivers, from 100G to 1.6T. He earned his Ph.D. in Physics from UNICAMP, Brazil, and completed a postdoctoral fellowship at the University of California, San Diego. He has co-authored over 80 publications in international journals and conferences on silicon photonics.
(TUT8) 22nd March 1:00-2:30 PM PST, Grand Ballroom Salon A
Introduction to SiC power MOSFET technology and reliability
Peter Moens (onsemi)
This tutorial provides the audience with insight into the reliability status of SiC power devices. The following topics will be addressed: Characterization of the SiC/SiO2 interface by charge pumping and ultra-fast BTI measurements Identification of the physical nature of the interface point defects through electrically detected magnetic resonance Gate Switching instability Gate oxide reliability (TDDB) and lifetime. Comparison of SiC/SiO2 to Si/SiO2Reverse bias reliability Cosmic ray susceptibility Short circuit withstanding time Bipolar degradation.
Peter Moens received a Master in nuclear physics and a Ph.D. in solid state physics from the University of Gent, Belgium, in 1990 and 1993 respectively. At onsemi he was responsible for the development of 600+V GaN based power devices (2009-2019). Since 2019, he is working on SiC MOSFETs. He is/was a member of the technical program committees of IEDM, ISPSD, IRPS, CSMANTECH, ICSCRM, IRW, EDTM, ESSDERC and ESREF. He was the General chair of ISPSD 2012. He authored and co-authored over 200 publications in peer reviewed journals or conferences, 20 invited papers, and is the recipient of 6 best paper awards (including 2 ISPSD best paper awards as first author). He presented tutorials on smart power reliability and GaN power device reliability at IRPS and ISPSD and contributed to 2 books chapters on GaN power devices and reliability. He is an inductee of the ISPSD International Hall of Fame. He holds 62 US patents.
(TUT9) 22nd March 1:00-2:30 PM PST, Catalina Ballroom
Fundamentals of Interconnect Reliability: Physics, Failure Mechanisms, and Qualification
Huai Huang (IBM)
As on-chip interconnect technology continues to scale to meet increasingly stringent power, performance, and area requirements, ensuring interconnect reliability remains a fundamental challenge in semiconductor development. This tutorial introduces the core concepts of back-end-of-line (BEOL) reliability and provides a structured overview of the key physical failure mechanisms affecting interconnects, including time-dependent dielectric breakdown (TDDB), electromigration (EM), stress migration (SM), and thermal cycling (TC). The tutorial emphasizes the underlying reliability physics, commonly used qualification methodologies, and practical process optimization approaches used to mitigate scaling-induced reliability risks. In addition, reliability considerations and qualification strategies for BEOL passive devices are covered.
Huai Huang is the Back-End-of-Line (BEOL) reliability lead engineer in IBM Semiconductor Technology Research and Development, covering advanced node BEOL qualification and future node interconnect reliability research. He joined IBM Research after earning his Ph.D. in Physics from the University of Texas at Austin in 2012. He has been focused on BEOL reliability research and development, and most recently on 2nm and beyond BEOL reliability. He has authored or co-authored over 40 publications and over 40 US patents, with over 1300 citations.
(TUT10) 22nd March 3:00-4:00 PM PST, Grand Ballroom Salon BC
What Can In-System Test and SLM Data Bring to the Reliability Community?
Adam Cron (Synopsys)
We will first explain foundational DFT concepts like DFT, ATPG, BIST, and IFS; then review other sources of systemic data like sensors and monitors. Next, we will take a brief look at how to extract these sources of information and use them in-system or for fleet monitoring, focusing on both SLM and DFT data sources. Lastly, we will look at a few case studies (e.g., cell characterization, and reliability prediction) and future trends.
Adam Cron is a Distinguished Architect at Synopsys working with customers worldwide on complex Test, Security, and Silicon Lifecycle Management tool flows and architectures for digital ICs. He has helped architect design-for-test, design-for-manufacturing, and security tools for several generations of products. As a Syracuse University Computer Engineering graduate, Adam also worked in test-related fields at Motorola and Texas Instruments where he got his first exposure to IEEE standards while designing the first ICs compliant to IEEE Std 1149.1. In the past, Adam has served as Chair or Vice-chair of the Test Technology Standards Committee overseeing the development of IEEE Test Standards for about a dozen years. Adam is Chair of IEEE Std 1838 which standardized 3D-IC test access; Editor of IEEE Std 1149.4 for a mixed-signal test bus; a member on many IEEE Test Standards working groups such as P1687, P1687.2, P2929, and P3405; an IEEE Golden Core recipient for long-standing service to the society; and recipient of the 2024 IEEE CS Hans Karlsson Standards Award, and the recipient of the 2025 IEEE SA Lifetime Achievement Award “for continuous and outstanding service to the standards development community in the field of electronic testing and design-for-test solutions.” He has authored several papers, articles, book chapters, and patents and is a frequent speaker or panelist at conference sessions held at events such as ITC and DAC.
(TUT11) 22nd March 3:00-4:00 PM PST, Grand Ballroom Salon A
Radiation Effects in Photonic Integrated Circuits
Adrian Ildefonso (Indiana University)
Photonic Integrated Circuits (PICs) are emerging as compact, efficient solutions for space-based communications, sensing, and navigation. As these technologies advance toward flight applications, understanding their response to radiation is increasingly important. This tutorial presents an overview of radiation effects on PICs, including total ionizing dose, displacement damage, and single-event effects. It examines how radiation impacts key components and summarizes recent experimental findings. Testing approaches and considerations relevant to space deployment will also be introduced.
Dr. Adrian Ildefonso is an Assistant Professor of Intelligent Systems Engineering at Indiana University Bloomington. He received a B.S. in Computer Engineering from the University of Puerto Rico at Mayagüez in 2014 and an M.S. and Ph.D. in Electrical and Computer Engineering from the Georgia Institute of Technology in 2017 and 2020, respectively. Before joining Indiana University, he was a research engineer and a Jerome and Isabella Karle Fellow at the U.S. Naval Research Laboratory in Washington, D.C., where he developed laser-based techniques to emulate radiation effects in microelectronic devices.
Dr. Ildefonso’s research focuses on radiation effects and reliability in advanced microelectronic and photonic systems, with an emphasis on laser-based single-event testing, radiation-hardness assurance, and predictive modeling of device behavior in extreme environments. He has published over 50 peer-reviewed journal articles and received several best paper awards. He is a Senior Member of the IEEE and the recipient of the 2024 Radiation Effects Early Achievement Award from the IEEE Nuclear and Plasma Sciences Society.
(TUT12) 22nd March 3:00-4:00 PM PST, Catalina Ballroom
Understanding Thermomigration: Experimental Insights and Reliability Considerations
Olalla Varela Pedreira (IMEC)
Thermomigration (TM) is a phenomenon that describes the movement of atoms caused by temperature gradients. Such phenomenon is becoming an important reliability concern in advanced technologies. As the device dimension shrinks, the power density increases and local self-heating coming from the BEOL or the transistor level, generates thermal gradients that can drive the atomic migration even without the presence of an electrical force. Traditional EM-based reliability often overlooks this effect, and this might lead to inaccurate interconnect lifetimes. In this tutorial we will review the physical mechanisms behind Thermomigration and its differences from Electromigration and Stress migration. We will highlight the difficulties of experimentally isolating TM: different test structures, low or no-current experiments, controlled thermal gradients....Additionally, we will highlight the need of the different modelling approaches needed to interpret the Thermomigration effects. Finally, we will discuss the implication of TM on the lifetime estimation. This work highlights the current progress and identifies open questions for integrating TM into next generation reliability frameworks.
Olalla Varela Pedreira received her M.Sc. in Telecommunication Engineering from the University of Vigo, Spain. She joined imec in 2007 as a Research Engineer working on the optical characterization of MEMS devices. From 2011 she expanded into 3D integration technologies, focusing on optical characterization of Cu pumping and related phenomena in TSVs . Since 2014, her research has focused on BEOL reliability, including electromigration, TDDB, and other interconnect reliability challenges in advanced metallization. She has co authored multiple publications on electromigration and metal drift in advanced interconnects and related reliability studies. In 2024, she became Team Leader of the Quality and Reliability Testing (QRT) team at imec, extending her expertise to the reliability and qualification of silicon photonics and other emerging technology platforms.
(TUT13) 22nd March 4:30-5:30 PM PST, Grand Ballroom Salon BC
Resiliency in Zetta-Scale AI Factories
Sanjay Gongalore (NVIDIA)
There are many challenges in operating modern datacenters reliably at scale. This tutorial presents some of the key resiliency issues due to growing datacenter complexity, including silent data corruption (SDC) and detected uncorrected errors (DUE) in AI factories, and hardware/software methods to minimize and mitigate such issues to maximize resource availability and job throughput.
Sanjay has more than 15 years’ experience architecting and implementing GPUs and has led multiple GPU and SOC projects from concept to production, addressing all aspects from functionality, performance, power, and RAS. His first resiliency project was architecting and verifying end-end fault detection schemes for a Fibre Channel Storage network switch at Brocade. Subsequently, he led the development and silicon validation of RAS features in NVIDIA’s first (and only) server chipset – nForce 5. He currently heads NVIDIA’s Resiliency and Safety Architecture team, with efforts focused on reliability and availability modeling; defining hardware and software optimizations to improve hardware reliability and minimize downtime/blast radius of hardware errors; and developing architecture diagnostics to identify hardware defects especially those causing silent data corruption. While this tutorial focuses on the datacenter, many of these concepts and solutions also apply to functional safety in autonomous vehicles – both automotive and industrial.
(TUT14) 22nd March 4:30-5:30 PM PST, Grand Ballroom Salon A
X-ray Microbeam Techniques for Probing Stress Induced Phenomena in Interconnects
Ping-Chuan Wang (SUNY New Paltz)
Synchrotron-based x-ray microbeam techniques have been employed to investigate the interplay between mechanical stress and various degradation mechanisms in microelectronics. For example, electromigration-induced stress development in metallization remains an intriguing subject and has significant implications for interconnect reliability. This tutorial will present case studies of x-ray microbeam analyses on electromigration-induced stress development in aluminum-based conductor lines, highlighting the unique capability of these techniques to elucidate the mass transport phenomena underlying degradation process.
Dr. Ping-Chuan Wang is an Associate Professor in the Division of Engineering Programs at the State University of New York (SUNY) at New Paltz. He received his doctorate degree in Materials Science and Engineering from Columbia University. Following a two-decade career in the semiconductor industry with IBM Microelectronics and GlobalFoundries, he joined SUNY New Paltz in 2018 to pursue academic freedom and his passion for educating the next generation of engineers and scientists. Dr. Wang pioneered synchrotron x-ray–based spatiotemporal characterization of electromigration-induced stress evolution and contributed to or led the qualification of several COMS, BiCMOS, and RF technology nodes during his industry tenure. At SUNY New Paltz, he greatly enjoys engaging with students through teaching and research, drawing on his expertise in microelectronics reliability and solid mechanics. His recent interests include materials science for additive manufacturing, engineering education, and interdisciplinary curriculum development.
(TUT15) 22nd March 4:30-5:30 PM PST, Catalina Ballroom
Heterogeneous Integration Reliability Challenges and Roadmap
Richard Rao (Marvell)
This tutorial is intended for experienced reliability professionals, technologists, and technical managers working on advanced ICs, chiplets, and system‑level integration. As heterogeneous integration (HI) becomes the dominant path for performance scaling, reliability physics is increasingly defined by multi‑die interactions, complex materials stacks, and package‑system co‑design. This tutorial focuses on practical reliability challenges, emerging failure mechanisms, and forward‑looking qualification strategies. 1. Introduction of Heterogeneous Integration Systems: The tutorial opens with an overview of modern HI platforms, including 2.5D/3D ICs, chiplet‑based architectures, hybrid bonding, and co‑packaged optics, etc. Emphasis is placed on how reliability ownership shifts from die‑level to package‑ and system‑level reliability physics, redefining traditional IRPS paradigms. 2. Heterogeneous Integration Reliability Challenges: Key challenges are discussed through a physics‑of‑failure lens, including: Thermo‑mechanical stress and CTE mismatch/Fine‑pitch interconnect fatigue and hybrid bond integrity/Electromigration and thermal migration /Warpage, delamination, and interface aging/Multi-physics and chip to package interactions. 3. Product Reliability Case Studies. Two representative examples are examined: Large‑Size, High‑Power AI Processor Chips: Reliability risks driven by extreme power density, thermal gradients, and package‑induced stress. Silicon Photonics Packages: Packaging technologies, optical alignment stability, thermal and stress sensitivity, etc; and silicon Photonics Reliability and Qualification Methodology. 4. Reliability Roadmap: 5‑Year and 10–15‑Year Outlook. The tutorial concludes with a forward‑looking reliability roadmap addressing emerging materials, AI‑assisted reliability prediction, digital twins, and evolving standards needed to support heterogeneous integration over the next 5 and 10–15 years.
Dr. Richard Rao is a Senior Principal Engineer and Technical Lead for Reliability Engineering at Marvell Technology, where he is responsible for advanced electrical and silicon photonic IC reliability. He is a Senior Member of IEEE and currently serves as Chair of the IEEE Heterogeneous Integration Roadmap (HIR) Reliability Working Group.
Prior to joining Marvell, Dr. Rao was a Technical Fellow at Microsemi/Microchip Corporation and a Consulting Engineer at Ericsson Inc. His career spans both industry and academia, with extensive experience in reliability physics, materials mechanics, and advanced semiconductor packaging. He previously held academic and research positions as an Associate Professor at the University of Science and Technology of China, a Research Fellow at Northwestern University (Evanston, IL, USA), and a Research Fellow at the National Science and Technology Board of Singapore.
Dr. Rao received his Ph.D. in Solid Mechanics of Materials from the University of Science and Technology of China. His work focuses on reliability challenges associated with heterogeneous integration, high‑power ICs, and photonic‑electronic co‑integration.
(TUT16) 23rd March 8:30-10:00 AM PST, Grand Ballroom Salon BC
3D-NAND Scaling and Reliability Challenges
Yoshiaki Fukuzumi (Micron Technology)
3D-NAND Flash Memory has been continuing bit density scaling of 36% annually, resulting in 30-fold increase over the past decade. With the advent of the AI era, the demand for scaling of bit density, performance, and cost are becoming even more stringent. This tutorial will begin with a brief overview of NAND Flash fundamentals, followed by a history and future outlook on 3D-NAND scaling. Additionally, it will address the reliability challenges that accompany these advancements.
Yoshiaki Fukuzumi received his B.S. and M.S. degrees in Applied Physics from the University of Tokyo, Japan, in 1994 and 1996, respectively. He began his career at Toshiba, where he worked on device and process development for DRAM, Floating-Body Cell, and MRAM technologies. Following his research on resistive RAM as a visiting scholar at Stanford University, California, he started the development of 3D Flash memory in 2006 and led the device and process development of 64-layer NAND project.
He joined Micron Technology in 2018 and currently serves as a Fellow in Advanced NAND Technology, leading the NAND technology team in Japan. His work focuses on NAND technology pathfinding, including cell device innovation, array architecture exploration, and process integration strategies to enable continued scaling in cost and performance.
(TUT17) 23rd March 8:30-10:00 AM PST, Grand Ballroom Salon A
Application of SRAM HTOL in Process Qualification and Improvement
Yuncheng Song (IBM)
In semiconductor process qualification, SRAM is frequently utilized as a Technology Qualification Vehicle (TQV) due to its dense architecture, which is highly sensitive to process variations and defects. High Temperature Operating Life (HTOL) serves as the primary stress test to demonstrate both intrinsic and extrinsic long-term reliability. By utilizing elevated voltage and temperature, HTOL simulates ten years of field operation in less than 1,000 hours. While HTOL primarily exposes thermally or voltage-activated extrinsic defects, it also reveals SRAM’s Vmin, which is caused by Bias Temperature Instability (BTI) induced Vt shift in cross-couple inverters. A successful HTOL qualification requires a thorough understanding of applicable JEDEC standards. This tutorial covers HTOL fundamentals, the statistical math behind JEDEC sample sizes recommendations, and practical examples of how HTOL can help technology improvements.
Yuncheng Song is an experienced semiconductor professional with over a decade of experience in hardware development and reliability engineering. He currently serves as a Hardware Developer at IBM, where he leads SRAM High-Temperature Operating Life (HTOL) qualification for advanced technologies. Prior to IBM, Yuncheng lead a product reliability team and spearheaded cross-functional initiatives involving memory solutions, process integration, advanced circuit design, and testing. His work ensured successful HTOL qualification for FinFET platforms and derivative technologies, while providing customers with degradation and screening guidelines based on HTOL data and mission profiles. He as major contributor resolved serval defect-induced failure modes in FinFET technologies, including rear extrinsic defects occurring less than 10 PPB (parts per billion)
Yuncheng’s expertise spans device physics, reliability physics, and advanced characterization techniques, supported by hands-on experience in cleanroom processing and statistical analysis. He earned his Ph.D. in Electrical Engineering from Yale University, focusing on monolithic integration of III-V optoelectronics with silicon, and holds both M.S. and B.S. degrees in Microelectronics from Peking University. His contributions to the semiconductor industry include multiple publications and patents in areas such as SRAM reliability, FinFET technology, and optoelectronic integration.
(TUT18) 23rd March 8:30-10:00 AM PST, Catalina Ballroom
Defect-Mediated Charge Trapping and Electrical Reliability in BEOL Amorphous Oxide Semiconductor Transistors with High-k Gate Dielectrics
Chadwin Young (University of Texas at Dallas)
This tutorial provides the foundation for an integration-oriented overview of back-end-of-line (BEOL) amorphous oxide semiconductor (AOS) thin-film transistors incorporating high-κ gate dielectrics, with a central focus on the use of electrical characterization to probe electrically active defects (i.e., traps), and their implications on performance and reliability assessment. Emphasis is placed on practical measurement methodologies – including DC current – voltage (I-V) characteristics, hysteresis analysis, bias-temperature stress, relaxation, and transient/pulsed techniques to isolate charge trapping contributions arising from the high-κ dielectric bulk, the AOS/high-κ interface, and possible process-induced traps caused by the relatively low-temperature fabrication limitation in BEOL integration. The tutorial further provides a defect-physics overview of amorphous oxide semiconductors, detailing the roles of oxygen vacancies, metal–oxygen coordination disorder, subgap tail states, and hydrogen-related defects in establishing semiconducting behavior, carrier transport, and stability. Particular attention is given to how these defects may evolve with deposition conditions, post-deposition treatments, and BEOL thermal budgets, and how they manifest as measurable electrical signatures such as threshold voltage shifts, mobility degradation, and time-dependent instability. By explicitly linking defect formation, charge-trapping mechanisms, and electrical observables, this tutorial equips semiconductor engineers and scientists with a cohesive framework for characterizing electrically active defects and understanding this to better evaluate and comprehend complex reliability challenges in BEOL-compatible AOS transistor technologies.
Chadwin D. Young received his B.S. degree in Electrical Engineering from the University of Texas at Austin in 1996, and his M.S. and Ph.D. degrees in Electrical Engineering from North Carolina State University in 1998 and 2004, respectively. In 2001, he joined SEMATECH, where he completed his doctoral dissertation research on high-k gate stacks and subsequently advanced to Senior Member of the Technical Staff. At SEMATECH, his work focused on the electrical characterization and reliability evaluation of high-k gate dielectrics for advanced device architectures, including planar silicon and InGaAs devices, FinFETs, and nanowire FETs. In September 2012, he joined the Departments of Materials Science and Engineering and Electrical and Computer Engineering and is currently an Associate Professor. His current research centers on the evaluation of emerging materials and devices – such as two-dimensional materials, amorphous oxide semiconductors, memristors, and β-Ga₂O₃ – through the development and application of advanced electrical characterization and reliability methodologies, integrated with physical characterization and modeling/simulation. He is the recipient of an NSF CAREER Award and has authored or co-authored over 310 journal articles, conference papers, and invited publications. He has served on the management and technical program committees of numerous international conferences, including ICMTS, IIRW, IRPS, SISC, IEDM, WoDiM, and SNW, and has served as Conference Chair for IIRW, ICMTS, and SISC. He is a former Guest Editor for IEEE Transactions on Device and Materials Reliability. He is currently a Senior Member of IEEE and serves on the Device Reliability Physics Committee of the IEEE Electron Devices Society.
(TUT19) 23rd March 10:30-11:30 AM PST, Grand Ballroom Salon BC
Application of Physics of Failure and Degradation in Extended Mission Profile Assessments
Rene Rongen (NXP)
On the journey towards autonomous vehicles, smart factories, and robotics-driven automation, semiconductor content in these complex systems is increasing rapidly. Cars, industrial equipment, and consumer applications with the latest advances today, will be antiquated tomorrow.
This accelerated innovation cycle introduces new reliability challenges. Traditionally, reliability research focusses on Physics-of-Failure, understanding failure mechanisms to improve reliability margin. However, the paradigm is shifting towards Physics-of-Degradation, which emphasizes monitoring and evaluating the gradual deterioration of components and systems.
René Rongen is a Fellow in Applied Reliability at NXP. Since joining Philips/NXP in 1997, he has built deep expertise in reliability physics, contributing across a wide range of technical and strategic roles. René plays a central role in shaping NXP’s reliability practices. He is the lead editor of the company’s Reliability Policy, owner of key product reliability test specifications, and the NXP Reliability Knowledge Framework. His influence extends beyond NXP through active participation in global standardization bodies such as AEC, JEDEC, and ZVEI.
Next to Vice-Chair of AEC, René is instrumental in the development and revision of key industry standards, including AEC-Q100, AEC-Q006, JESD47, and the ZVEI Handbook for Robustness Validation. His work helps ensure reliable, high-quality semiconductor products across the electronics industries.
René is also a contributor to the technical reliability community. He has (co-)authored numerous papers on Cu-wire reliability, solder joint performance, challenges wafer-level CSP devices and lately electric parameter drift due to package aging. He is active at leading conferences—including IRPS, ESREF, ECTC, and the AEC Reliability Workshop—as a speaker, paper presenter, and technical committee member. In 2023 and 2025 he chaired the AEC Reliability Workshop under the umbrella of the ESREF conference.
From 2005 to 2018, René supported the Dutch Accreditation Council as a reliability test specialist, contributing to the ISO/IEC 17025 accreditation of reliability laboratories across the Netherlands.
(TUT20) 23rd March 10:30-11:30 AM PST, Grand Ballroom Salon A
SRAM qualifications for automotive applications
Christian Schluender (Infineon Technologies AG)
The focus in this tutorial will be on SRAMs for automotive applications and the way the high requirements are qualified. Large memory sizes, low failure rates and very wide temperature ranges demand extremely low probabilities of defective cells.
Non-functional cells are caused by defects during processing (0h, extrinsics) and by aging of the memory circuits (intrinsics). Time-Dependent-Variability in particular poses a major challenge with the small structure sizes of current technologies. Additionally, radiation can induce data losses during operation (Soft Errors). Increasingly complex circuit countermeasures have been developed for all these sources of error. To ensure the automotive quality, a large number of SRAM components are stressed with increased operating voltages at high temperatures (HTOL). Statistical methods are used to evaluate the measurement data in order to e.g. determine a single-bit error probability.
Dr. Christian Schlünder has received his Dipl.-Ing. (1999) and his doctoral degree in engineering science (2006) accompanying his regular work (both from TU Dortmund, Germany). He started his career at Siemens Central Research Labs. Then he joined Infineon Technologies and worked for the Corporate Technology Reliability Group.
Today, as a Lead Principal Engineer, he manages post-silicon component qualifications for in-house IPs, 3rd party IPs and transfers to silicon foundries worldwide.
Furthermore, he supervises frequently graduating and PhD students in close cooperation with different Universities. His current methodology work is focussed on time dependent variability and its impact on digital and analog mixed-signal applications.
Christian is author / co-author of more than 60 publications (incl. several Best Paper Awards) and has written a book chapter (Springer Publishing) on Hot Carrier Stress in different circuit applications. Additionally, he has presented invited talks and tutorials at many international reliability conferences. He is frequently a member of the Technical Program Committee of the IEEE-conferences ‘IRPS’ & ‘IIRW’ and acts as a reviewer for microelectronic journals.
(TUT21) 23rd March 10:30-11:30 AM PST, Catalina Ballroom
Bias Temperature Instability in BEOL-Compatible Oxide Semiconductor Transistors for Ultra-High-Density Monolithic 3D ICs
Xiao Gong (National University of Singapore)
Back-end-of-line (BEOL)-compatible oxide semiconductor transistors are promising technology enablers for future high-density, high-performance, and energy-efficient monolithic 3D integrated circuits. However, one of the key challenges is bias temperature instability. This talk presents a comprehensive overview of recent progress in understanding and enhancing the reliability of oxide semiconductor field-effect transistors (OSFETs). We systematically investigate key degradation mechanisms—including positive bias temperature instability (PBTI), negative bias temperature instability (NBTI), and low-frequency noise (LFN)—under both DC and AC stress conditions. Our studies reveal the strong dependence of device stability on factors such as channel thickness, material composition, and stress waveform parameters like frequency and duty cycle. In particular, we highlight the critical role of hydrogen-related effects and their modulation by electrical stress. Furthermore, we demonstrate how reliability can be significantly improved through structural innovations, such as tri-layer channel stacks and surface/interface engineering techniques. These findings offer valuable insights into the physical origins of instability and provide practical design strategies for enabling robust, high-performance OSFETs tailored for monolithic 3D integration and BEOL-compatible applications.
Dr. Gong Xiao is currently the GlobalFoundries Chair Associate Professor in the ECE Department of the National University of Singapore (NUS). He obtained his Ph. D Degree from NUS in 2023 and was a Visiting Scientist at MIT in the year of 2014. His research interest includes advanced transistors and emerging memories for in-memory computing, monolithic 3D integration, opto-electronic integrated circuits and their applications in quantum technology, as well as ultra-high frequency and ultra-wide bandgap device technology. He has won many awards, including the Bronze Medal at the 6th TSMC Outstanding Student Researcher Award, the Best Student Paper Award at VLSI Symposium (2017, 2021, and 2024), the Best Demo Paper Award at VLSI Symposium (2022, 2023, 2025), the Best Student Paper Award at ICICDT (2019, 2021, 2023, and 2024), Emerging Leaders in Journal of Physics D 2021, and NUS Engineering Teaching Excellence Award (2018, 2023, and 2024). He has more than 430 publications in international journals and conferences, including more than 120 papers in IEDM and VLSI Symposium. He is the Technical Program Chair in SISC (2025)and ICICDT (2019, 2022, 2023, 2024), and Sub-committee Chair in ICICDT (2021) and EDTM (2022, 2023, 2025, and 2026), and in the technical committees of IEDM (2021, 2022), IMW (2025, 2026), VLSI-TSA (2022, 2023, 2024, 2025, 2026), ECS (2014, 2016, 2018, 2020, 2022, 2024, and 2026), ICMAT (2017), EDTM (2017 to 2021, 2023), IWJT (2021, 2023), etc. He is the Editor of IEEE Electron Device Letters.
(TUT22) 23rd March 1:00-2:30 PM PST, Grand Ballroom Salon BC
BTI Reliability in CMOS Technologies: Degradation Physics, Process interactions, and Modeling Challenges
Narendra Parihar (Intel)
Bias Temperature Instability (BTI) aging in CMOS transistors—particularly Negative BTI (NBTI) in PMOS—remains a major reliability challenge as the industry advances toward gate-all-around technologies. This tutorial provides a detailed exploration of BTI fundamentals and degradation mechanisms, focusing on how process integration choices, material properties, and device scaling modulate BTI effects. We review state-of-the-art modeling methodologies, addressing time, voltage, and temperature dependencies, and present acceleration and extrapolation strategies to ensure accurate long-term device and circuit reliability.
Dr. Narendra Parihar earned his Ph.D. in Electrical Engineering from the Indian Institute of Technology Bombay in 2018. In 2019, he joined IMEC, Belgium, as a device researcher, focusing on advanced CMOS device engineering. He has authored more than 40 publications in peer-reviewed journals and international conferences, and has contributed to multiple book chapters. Dr. Parihar has actively served on the technical program committees of several IEEE conferences. Since 2022, he has been part of Intel’s Foundry Quality and Reliability Pathfinding team, where his work centers on advancing front-end reliability modeling for Intel’s cutting-edge technologies.
(TUT23) 23rd March 1:00-2:30 PM PST, Grand Ballroom Salon A
Design and Reliability of Ferroelectric Capacitor Memories
Kai Ni (Notre Dame University)
Ferroelectric memories—particularly capacitor-based architectures—are emerging as a frontrunner for high-density, low-power storage in the evolving AI landscape. These designs offer a compelling combination of low-voltage operation, high-speed performance, and robust reliability, leading to significant advancements across the research community. In this tutorial, we will explore various ferroelectric capacitor memory configurations, examining their architectural design and the critical reliability challenges they face.
Kai Ni received the B.S. degree in Electrical Engineering from University of Science and Technology of China, Hefei, China in 2011, and Ph.D. degree of Electrical Engineering from Vanderbilt University, Nashville, TN, USA in 2016 by working on advanced electronics for space applications. Since then, he became a postdoctoral associate at University of Notre Dame, working on ferroelectric devices for nonvolatile memory and novel computing paradigms. He joined Electrical and Microelectronic Engineering department at Rochester Institute of Technology as an assistant professor in 2019. After four years, he joined University of Notre Dame as an assistant professor in the Electrical Engineering department in 2023. He has more than 100 publications in top journals and conference in nanoelectronics. His current interests lie in nanoelectronic devices empowering next generation storage and computing hardware technology.
(TUT24) 23rd March 1:00-2:30 PM PST, Catalina Ballroom
Challenges in Gate Stack Integration, Defectivity, and Reliability of 2D Material FETs
Quentin Smets (IMEC)
Two-dimensional (2D) materials, particularly Transition Metal Dichalcogenides (TMDCs) offer new opportunities for CMOS scaling due to their atomic thinness, self-passivated nature and van der Waals interfaces. Yet, these features introduce critical challenges for gate stack integration and defect control. This tutorial reviews gate stack integration and dielectric deposition approaches, defectivity and reliability characterization techniques, and outlines benchmarking strategies essential for assessing process maturity towards industrial adoption of 2D FET technology.
Quentin Smets is a Senior Researcher at imec (Leuven, Belgium), specializing in field effect transistors with 2D material channels. He received his M.Sc. and Ph.D. degrees in Electrical Engineering from KU Leuven, where he investigated tunnel FETs with III-V semiconductors. He now leads efforts to bring semiconducting 2D materials into a CMOS-compatible 300 mm production flow. His work focuses on novel modules for channel, gate stack, and contacts, implemented in imec’s 300 mm pilot line. As device engineer, he develops the electrical characterization methodology and investigates device performance, scaling, variability, and reliability. He has authored and co-authored multiple publications in leading journals and conferences, including IEDM and VLSI.