2024 Workshops
Inside Program: Conference Program l Keynote Speakers l Tutorials
Workshops l Year in Review l Highlight Papers | Invited Speakers
Workshop1: Circuit Aging Simulation - Challenges and Solutions
Moderator: Souvik Mahapatra (IIT Bombay) and Jyotika Athavale (Synopsys)
Abstract: FETs in modern day circuits are impacted by several aging mechanisms such as Bias Temperature Instability (BTI) and Hot Carrier Degradation (HCD), thereby resulting in circuit (and eventually product) performance degradation. Presently, EDA vendors have circuit aging modules as part of their SPICE circuit simulator offering, and their customers (IDM, or Foundry, in a Foundry-Fabless ecosystem) provide necessary aging models. These models are required to estimate aging of FET parameters (and therefore of the circuit under consideration), for a particular mechanism, under applied biases and temperature profiles. There are several challenges to develop suitable (device level) aging models. BTI recovers when the stress is removed, while HCD does not. HCD has a complex dependence on terminal biases and temperature. During device level stress for HCD, the data are often convoluted due to BTI, especially for PMOS. The impact of self heating is very different during device level DC versus circuit level AC (pulsed) conditions. It is difficult to measure the full suite of I-V and C-V curves after BTI stress (due to recovery impact), hence development of aged models is challenging. There are several challenges that need to be addressed for proper circuit aging simulation. The type of circuit (digital or AMS, logic depth, etc.) and application under consideration (mission profiles) determine the bias profiles and associated temperature profiles (due to self heating, when applicable) experienced by the FETs of the circuit. BTI recovery is complex and difficult to model under random activity (bias and temperature profiles) encountered in such realistic cases, the situation becomes even more challenging under Dynamic Voltage Frequency Scaling (DVFS) scenarios. HCD has a complex dependence on terminal biases and temperature, and although recovery is not an issue, the modeling can become challenging under DVFS conditions. Blanket or Age (effective duty) based approaches might not always give best results. This workshop aims to discuss the above challenges and find out possible solutions, in order to develop a reliable Silicon-to-Simulation framework. We expect active participation from Foundry, Fabless, IDM and EDA industries, and academia.
Workshop2: Reliability Aware EDA (BEOL / Heating)
Moderator: Markus Herklotz (GlobalFoundries) , Baozhen Li (IBM)
Abstract: Design verification flows for advanced applications, such as for ATV, typically use quite stringent sign-off criteria wrt temperature and lifetime. Within such markets so called temperature mission profiles are quite common, however typically are provided by the OEM as an ECU-ambient profile and must be refined by subsequent tiers to reveal the actual substrate (or junction) temperature profile. In today’s large supply chains this refinement might lead to cascading pessimism gaps and massive overdesign. Semiconductor vendors may locally refine the temperature mission profile by proper consideration of self- and joule-heating but are dependent on an exact definition of reference points, where the temperature mission profile was defined.This workshop should address the challenges wrt to temperature mission profile from supply chain bottom-up perspective and should provide a sensitivity for proper definition of EDA sign-off conditions. Following questions may be discussed:
How may semiconductor vendors use a temperature mission profile for their intrinsic qualification and proposed EDA sign-off conditions?
What is required to refine the MP and to enable a proper sign-off criteria, e.g. for EDA-EM analysis?
Package impacts design – which (conservative?) boundary conditions must be assumed?
How EDA-current limits are defined to limit the interconnect metal joule heat – what are the limitations, and can we exceed the typically defined 5K-Irms limit?
What are the gating limitations to pass the EDA-EM verification? Idc_avg or Irms?
Workshop3: PID - Well Charging in product design: measurements, rules, challenges, DRC
Moderator: Andreas Martin (Infineon), Elodie Ebrard (GlobalFoundries) and Matthew Hogan (Siemens)
Abstract: Plasma processing induced charging damage (PID) from well charging is often only partially covered by design rules in the design manual. This leaves the risk on the product design open, since a lot of catastrophic fails have been reported in the literature. Well charging is a separate failure mode to the known and controlled gate antenna charging.
What is required for comprehensive well charging rules?
What needs to be tested during process qualification for the characterization of well charging?
What are the worst case structures?
What kind of protection can be used?”
What reliability stress measurements are required?
How can an antenna-DRC (design rule checker) being coded on the basis of existing EDA tools to achieve a technical concept which covers all risks of the product design?
What layout properties need to be considered for such an antenna-DRC?
Do EDA rules need to include path-based PID considerations?
Workshop4: Increasing urgency of GaN reliability physics development and standardization
Moderator: Sandeep Bhal (Texas Instruments) and Sameh Khalil (Infineon)
Abstract: Physics is a key enabler for market success; it is through the understanding of the failure mechanisms that we are assured of lifetime and quality. It is through industry alignment via standards committees like JC70 that we build industry consensus and confidence. We will motivate the discussion with key topics related to intrinsic and extrinsic reliability. For example, in fast-switching devices for power conversion, there is ringing. How do you assure reliability to a ring on every cycle? Another is the challenging topic of extrinsic reliability. For example, what are the acceleration factors, what are the best practices, what can we learn from Si.
Workshop5: RAS (Reliability, Availability, and Serviceability) in the Data Center
Moderator: Amr Hagag (ARM) and Saurabh Agrawal (Microsoft)
Abstract: The scale of the datacenters of today pose unique challenges for reliability engineers. It is important to understand those and work collectively on mitigation options. Workshop will discuss how to best measure Reliability, Accessibility and Serviceability (RAS) to provide the best possible experience to users. Special focus will be given to the issue of silent data corruption (SDC) possible root causes and mitigations.
Workshop6: Technology scaling challenges: Power vs Reliability
Moderator: Zakariae Chbili (Intel) and Pei-Jean Liao (TSMC)
Abstract: Ever since the introduction of Moore’s law, technology scaling has been driving the semiconductor industry to provide the increasingly performing products that power every aspect of our lives. After a first phase dominated by Dennard scaling in the 80s and 90s, scaling entered a second phase with the introduction of material and architectural changes such as high-k and FinFETs. With the introduction of nano-ribbons (GAA) and CFET architecture, a new phase of scaling has started where dimensional and vertical scaling is resumed, requiring several optimizations to mitigate the increase in power density. Thus, the need for improved low voltage performance becomes more and more important together with the lowering of Vmin and Vnom and the reduction in RC, as well as the need for improved modeling and management of thermals. Additionally, the resumption of dielectric scaling is also increasing the challenge for gate-field driven reliability mechanisms such as Time Dependent Dielectric Breakdown (TDDB), Bias Temperature Instability (BTI) and Hot Carrier Injection (HCI). This workshop aims at gathering key participants from the semiconductor ecosystem including foundry and fabless leaders as well as EDA leaders to discuss the direction of technology scaling and the important role played by reliability to enable or slow down this transition.
Workshop7: Impact of Self-Heating and HC/BTI interaction to Conductive Channel Hot Carrier Characterization and Modeling in Advanced CMOS Scaling (FinFets, NanoSheets, BSPDN, etc).
Moderator: Huimei Zhou (IBM) and Andreas Martin (Infineon)
Abstract: The extensive research activity carried out in recent years in the field of Conductive Channel Hot Carrier (CCHC) suggests the need of new stress/test methodologies to accurately characterize and model the CCHC degradation. With recent advanced CMOS technologies development (FinFets, Fully Depleted SOI, nanosheets, BSPDN, etc.) the following two key observations, in fact, challenge an accurate characterization of CCHC using traditional DC WLR HC stress/test methodologies (see current Jedec standards, as reference).
An increase in the role of channel Self-Heating (SH) during accelerated DC WLR CCHC stressing is expected with consequent dependence of the channel temperature (Tstr ) on the Vgs@str, Vds@str bias conditions. Typically, we expect Tstr >> Ttst (Test Temperature) >> Tuse (Average Temperature at use conditions) for a given ambient (Chuck) temperature at stress.
A possible BTI/HC interaction could be active during DC CCHC accelerating stressing due to self-heating. In this case the estimated %Idsat (typically used as a measure of the CCHC damage) has two contributions respectively from the BTI and the pure CCHC aging.
If minimum self-heating is expected at use conditions, the %Idsat shift effected by the combination of SH and induced BTI/HC interaction during accelerated DC stressing will project to the wrong EOL if not carefully taken care of.
The intent of this workshop is to discuss the challenges associated to the SH increase and BTI/HC interaction for a correct CCHC characterization and their impact to the End of Life projection.
Is only a DC WLR at accelerated conditions adequate?
Any specific requirements for an appropriate DC WLR characterization (Device Layout, Stress conditions, Chuck temperature modulation)?
Are additional CCHC stress/test solutions (AC HC, Package level stress, etc) needed to maximize the role of the pure CCHC contribution to %Idsat shift, by minimizing as much as possible the role of Self-heating and BTI/HC interaction?
Which Combination of CCHC stress/test methodology (1.→3.) should be considered for the correct EOL CCHC projection?
Outcomes of this workshop will be considered in a starting Jedec activity to define a CCHC standard needed in the industry with CMOS scaling. Your participation to this JC14.2 Activity is recommended.
This topic will be part of the JC14.2 meeting after IRPS (4/19).
Workshop8: Challenges in RF/mmW/5G
Moderator: Purushothaman Srinivasan (GlobalFoundries) and Sriram Kalpat (Qualcomm)
Abstract: The purpose of this workshop is to encourage a healthy and open debate on reliability considerations that are required and need to be considered when specific technology is chosen for 5G FR1/FR2 spectrum and for “beyond-5G” applications in FR3 spectrum. Considering EIRP requirements for handset and infrastructure, both CMOS and III-V technologies can meet the power requirement at lower cost for this application space. III-V technologies can be scaled in terms of handling lower power while CMOS_SOI can be scaled up to handle higher power. But they are vastly different in terms of reliability due to their material properties and device designs. Lifetime specifications based on the product and mission profiles and consideration on RF reliability and thermal (self-heating) behavior of these technologies play a key role. This workshop is intended to discuss these RF lifetime and reliability aspects for “beyond-5G” FR3 applications.
Workshop9: ESD EDA: What Can be Done Now and in the Future?
Moderator: Michael Khazhinsky (SiLabs) and Matt Hogan (Siemens)
Abstract: The verification of ESD protection in modern integrated circuits is a difficult challenge. There are several factors including increasing design and process complexity, higher-pin counts, use of mixed voltages, power management, etc. that make ESD analysis especially challenging. EDA checking/verification tools to design for effective ESD protection are getting used more and more. This includes schematic and layout-based checks, including current density (CD), point-to-point (P2P) resistance analyses, simulation-based methods, like SPICE compact model simulations, and Technology CAD (TCAD). Other EDA checks include verification on package and system level. All these checks are part of the ESDA Technical Report 18 for ESD Electronic Design Automation Checks. This report has been first published in 2011 and is now being revised.
Workshop10: (WS10) Functional Safety: Industrial, Automotive and AI
Moderator: Paula Chen (AMD) and Robert Jin (NXP)
Abstract: Functional safety, as per definition of ISO26262, IEC61508 and others, is demanded by regulation to mitigate unacceptable risks caused by electronic devices, IC, and systems. With the continued electrification, automation of machinery and road vehicles, artificial intelligence (AI) is being ubiquitously deployed to enable sensing, understanding, and reacting of electrical system to complex and dynamic situations, which in turn poses new challenges and risks for functional safety, such as ensuring the reliability, robustness, and explainability of AI systems, as well as addressing ethical, legal, and social implications. This workshop is aimed at forming discussion on but not limited to:
Evolution of functional safety standards and the impact
Uniform base failure rate (BFR) calculation and methodology
Specific requirements in automotives vs industrials vs medical applications
How to achieve functional safety at organization level?
How to achieve functional safety in a cost-effective manner (hardware + software)?