Keynote Speakers


IRPS 2026 Keynote Speakers



Advancing 3DIC Technologies to Propel AI Innovations

Dr. Jun He
Vice President of Advanced Packaging Technology and Service, TSMC

Biography: Dr. He is TSMC’s VP of Advanced Packaging Technology and Service, bringing over 30 years of semiconductor experience. He oversees 3DIC packaging manufacturing and testing, and his team has rapidly expanded CoWoS capacity for AI, improving 3DIC yield and cycle time. They consistently ramp new backend technologies for HPC and mobile markets. He also focuses on growing TSMC's 3DIC manufacturing network through OSAT partnerships and, by working with suppliers, offers customers a comprehensive 3DIC service, accelerating product time-to-market and HVM.

Dr. He joined TSMC in 2017 as Senior Director of Advanced Technology Q&R, where he developed methods to detect and screen reliability defects, speeding up 7nm and 5nm production. In 2019, he revamped TSMC's quality system for incoming materials and strengthened supplier relationships. Promoted to VP of Q&R in 2020, he built a foundry ecosystem covering material qualification, process/IP reliability, manufacturing quality, and customer product qualification, supporting 3nm development and ramp. He holds 141 global patents (60 US) and has published over 50 papers. He earned his B.S. in Physics and Ph.D. in Materials Science from the University of California, Santa Barbara.

Abstract: AI innovation has significantly boosted the demand for advanced packaging, particularly 3DIC solutions. These offer numerous benefits, including cost efficiency, design flexibility, and enhanced system performance. However, as AI product introduction accelerates towards an annual cadence, this presents unprecedented challenges related to fast development cycle times, steep manufacturing ramping, and stringent in-field low DPPM requirements. Therefore, ecosystem partnerships among chip designers, chiplet integrators, tool/material suppliers, HBM/substrate industries, and system providers are essential to continue advancing 3DIC packaging technologies for AI applications.


Reliability and High Performance Computing – lessons from the bleeding edge

Dr. Bruce Hendrickson
Principal Associate Director for Computing, Lawrence Livermore National Laboratory

Biography: Bruce Hendrickson is the Principal Associate Director for Computing at Lawrence Livermore National Lab (LLNL). In this role, he leads the largest computing organization in the U.S. national lab system with over 1400 employees, and he hosts the world’s fastest computer. He has spent his entire career in DOE labs, focused on mathematics, algorithms and architectures for large scale simulation and data science. His current responsibilities include oversight of aspects of LLNL’s extensive research programs in mathematics, computer science, data science and AI.

Dr. Hendrickson has degrees in Math and Physics from Brown, followed by a PhD in Computer Science from Cornell. His research has resulted in over 100 publications and garnered a number of international awards. He is a Fellow of the Hertz Foundation, the Society for Industrial and Applied Mathematics and the American Association for the Advancement of Science.

Abstract: High Performance Computing (HPC) is one of the most demanding environments for microelectronics. Leadership-class HPC systems involve 10s to 100s of thousands of processing units working in a tightly integrated fashion to provide exquisite insight into scientific and engineering questions. The scale and density of these systems require meticulous attention to power and thermal management.

In this talk, I will use El Capitan – the world’s fastest HPC system – as an exemplar to discuss some of these challenges and the solutions the community has developed to address them. Recurring themes will include very careful design and engineering practices, redundancy in key subsystems, and tightly coupled hardware/software co-design. I will finish by sharing examples of how cutting-edge simulations can provide insights that improve the design and reliability of high-consequence technologies.


Technology Strategies for Evolving Compute Challenges

Dr. Sri Samavedam
Senior Vice President, Semiconductor Technologies and Pathfinding, imec

Biography: Sri Samavedam is Senior Vice President of Semiconductor Technologies and Pathfinding at IMEC, Leuven, Belgium. Prior to joining IMEC in 2019, he was Senior Director of technology development at Globalfoundries, Malta, NY, where he led qualification of 14nm FinFET technology and derivatives into volume production and early development of 7nm CMOS. He began his career at Motorola working on strained silicon, metal gates, high k dielectrics and fully-depleted SOI devices. He holds over 50 U.S. patents and has co-authored more than 100 publications. He has a Ph.D. in Materials Science and Engineering from MIT, a Master’s degree from Purdue University and a Bachelor’s degree from Indian Institute of Technology.

Abstract: The rapid proliferation of large language models and agentic AI-driven applications continue to fuel an unprecedented demand for compute across datacenters and edge systems alike. The deceleration of CMOS scaling—yielding diminishing improvements in power, performance, area, and cost (PPAC) from node to node—and the escalating costs of new designs and wafer manufacturing, present a dual challenge for compute ecosystem. Addressing these constraints requires rethinking the problem from a tops-down, system-level perspective, where new approaches beyond traditional scaling may be required. This talk will explore key bottlenecks limiting compute system performance: compute density, power delivery and efficiency, thermal management, and memory capacity and bandwidth. It will highlight emerging technology strategies to overcome these barriers – continued dimensional scaling, novel device architectures, new materials and innovative integration schemes using advanced interconnect technologies. Introduction of these options will need deeper understanding of failure modes with new reliability considerations. This will also require fresh approaches to failure modelling and system robustness to ensure sustained performance throughout the operational lifetime.


Data Center Reliability: What Have We Learned?

Dr. Vilas Sridharan
AMD Senior Fellow, AMD, Inc.

Biography: Vilas Sridharan is an AMD Senior Fellow where he leads the RAS (Reliability, Availability and Serviceability) Architecture team. His research focuses on the modeling of hardware faults and architectural and micro-architectural approaches to reliability and fault tolerance in high-performance microprocessors. Vilas received his Ph.D. and M.S.E. from the Department of Electrical and Computer Engineering at Northeastern University, and his B.S.E. in Computer Engineering from Princeton University in 2000. From 2000 – 2004, he worked in the SPARC server division at Sun Microsystems. Since 2010, he has been on AMD’s RAS Architecture team.

Abstract: This talk will cover the challenges, current state, and future directions of addressing the needs of data center reliability.


Archives

IRPS 2025 Keynote Speakers

  • Min Cao, Vice President of Pathfinding and Corporate Research, TSMC

  • Choon Lee, SVP, GM of ATTD, Intel Corporation

  • Elif Balkas,, Chief Technology Officer, Wolfspeed

  • Shankar Venkataraman, Vice President and General Manager, Semiconductor Products Group, Applied Materials, Inc

IRPS 2024 Keynote Speakers

  • Shinichi Takagi, Professor, The University of Tokyo (Japan)

  • Su Jin Ahn, EVP, Advanced Technology Development Office at Samsung Semiconductor R&D Center, Samsung

  • Rajeev Malik, Program Director, Systems Development & Deployment, IBM Quantum

  • Sameer Pendharkar, Vice President of Advanced Technology Development, Texas Instruments

IRPS 2023 Keynote Speakers

IRPS 2022 Keynote Speakers

IRPS 2021 Keynote Speakers