Invited Speakers
Inside Program: Conference Program l Keynote Speakers l Tutorials
Workshops l Year in Review l Highlighted Papers | Invited Speakers
| Topic | Speaker | Title |
|---|---|---|
| GaN Devices | Tetsuo Narita (Toyota) | Design Principles of Metal-Oxide-Semiconductor Structures for Vertical GaN Power Devices |
| Memory Reliability | Tomoya Sanuki (Kioxia) | Reliability of 3D Flash Memory Under Cryogenic Operation for Bit Cost Scaling and Long-term Usage |
| Packaging and 2.5/3D Assembly | Tz-Cheng Chiu (National Cheng Kung University) | Effect of inelasticity on the cracking of materials and interfaces in heterogeneous integration |
| Packaging and 2.5/3D Assembly | Stefaan Van Huylenbroeck (imec) | Wafer to Wafer hybrid bonding pitch scaling challenges |
| Radiation Effect Reliability | Chang Goo Kang (Korea Atomic Energy Research Institute) | Correlation Between Interface Engineering and Radiation Hardness of Nanoscale Devices |
| SiC Devices | Filippo Giannazzo (CNR-IMM) | Two-dimensional Materials and Wide Bandgap Semiconductors: integration challenges and novel device applications |
Design Principles of Metal-Oxide-Semiconductor Structures for Vertical GaN Power Devices
Tetsuo Narita (Toyota)
Abstract: To get GaN MOSFETs with high performance and reliable operation, traps and charges at oxide/nitride interfaces should be controlled. Insertion of thin crystalline AlN interfacial layers at oxide/nitride interfaces not only enhanced the channel mobility by reducing electron trapping but also suppressed bias instability of threshold voltages. Furthermore, the roles of AlN are different in between c-plane and m-plane channels. We thus discuss the design principles of reliable and high performance vertical GaN MOSFETs.
Biography: Tetsuo Narita, Ph.D., joined Toyota Central R&D Labs., Inc. as a senior researcher in 2007 and Nagoya University, Japan as a Visiting Professor since 2024. Dr. Narita specializes in the growth for III-nitride power devices, focusing on the use of metalorganic vapor phase epitaxy. He has published 113 peer-reviewed journal articles on semiconductor growth and analysis and served as Project Vice-Manager for the Consortium for GaN Research and Applications, Working Group on Crystal Growth.
Reliability of 3D Flash Memory Under Cryogenic Operation for Bit Cost Scaling and Long-term Usage
Tomoya Sanuki (Kioxia)
Abstract: We believe low-temperature operation is key to future bit cost scaling. We report a 3D flash memory operating at 77 K that stores 7 bits per cell, enabling the highest bit density ever recorded. Data retention, read and program noise, and degradation from program/erase cycles are greatly improved. This technology can be combined with recovery annealing to reuse end-of-life chips. Semi-permanent use of ultra multi-level cells at cryogenic temperatures is promising for future storage devices.
Biography: Tomoya Sanuki received his M.Sc. degree in physics from Osaka University, Japan. In 1999, he joined Toshiba Corporation, where he was engaged in research and development of advanced CMOS logic, embedded DRAM, and system LSI at the Device Technology Laboratory. In 2010, he became a device engineer in a joint development project on CMOS logic with IBM in New York, USA. He was engaged in FEOL and transistor device engineering for high-performance CMOS devices with MGHK. In 2015, he became a researcher and device engineer at the Institute of Memory Technology R&D, where he was involved in the development of magnetic RAM, next-generation 3D flash memory, and future device technologies. Since 2024, he has been a senior researcher and strategist at the Frontier Technology R&D Institute in KIOXIA. He has 100+ U.S. patents issued or pending in the area of new semiconductor devices, and has authored or co-authored 28+ publications in IEDM, VLSI, EDTM, IMW, JXCDC, and J-EDS. He has also served on technical committees at various conferences including IMW, VLSI-TSA, EDTM, and DtDA.
Effect of inelasticity on the cracking of materials and interfaces in heterogeneous integration
Tz-Cheng Chiu (National Cheng Kung University)
Abstract: A challenge in evaluating the mechanical reliability of heterogeneously integrated packages is associated with the dense arrangements of dissimilar materials. In the evaluation of cracking or debonding risks under typical thermal stresses, the scale-dependent inelastic behaviors of these materials lead to distinctively different energy dissipation mechanisms. This paper presents a fracture-mechanics based approach for considering the effects of these time- and temperature-dependent inelastic characteristics on the failure driving forces and the design implications.
Biography: Tz-Cheng Chiu received the Ph.D. degree in mechanical engineering from Lehigh University in 2000. He is currently a Professor of the Department of Mechanical Engineering at National Cheng Kung University in Taiwan. His research interests are on material characterization and reliability simulation for advanced packages, in particularly in the areas of fracture mechanics, nonlinear mechanical behaviors, and finite element simulation.
Wafer to Wafer hybrid bonding pitch scaling challenges
Stefaan Van Huylenbroeck (imec)
Abstract: Imec reported the past years on the wafer-to-wafer hybrid bonding pitch scaling down to 200nm. This paper discusses specific yield improvement challenges attributed to this sub-micron scaling, such as wafer-to-wafer bond alignment accuracy, global and local wafer topography control by CMP ensuring void free hybrid bonding, electro-chemical copper corrosion of hybrid pads connected to long metal lines, surface-diffusion-driven copper bulge-out mechanisms, dielectric breakdown and copper diffusion along the bonding interface.
Biography: Stefaan Van Huylenbroeck is working in the 3D integration group of imec, a renowned research center based in Leuven, Belgium, specializing in advanced microelectronics and nanotechnology innovations. He received his MSc degree in Industrial Sciences - Electronics Engineering in 1990 and joined imec immediately afterwards, where he was first active as a device characterization engineer for digital CMOS technologies. Later, he moved towards the process integration and implementation of analogue modules in the core CMOS technology and was for more than 10 years involved in the development of high-speed and low-power bipolar and BiCMOS technologies, implementing Si BJT and SiGe HBT bipolar devices. He was also leading the process integration of Si VDMOS power devices. After joining the 3D integration team, he became responsible for the development and integration of via-middle and via-last through silicon via (TSV) modules. Over the last years, his major activity is focusing on the integration and scaling of wafer-to-wafer hybrid bonding technologies and the implementation of these technologies into bilateral projects.
Correlation Between Interface Engineering and Radiation Hardness of Nanoscale Devices
Chang Goo Kang (Korea Atomic Energy Research Institute)
Abstract: The mechanism of gamma-ray irradiation on the electrical variations of molybdenum disulfide (MoS2) field-effect transistors with buried local-back gate structure and the radiation hardness of high-energy protons in 3.5nm thickness of ZnO TFTs were investigated and concluded that the device instability mainly caused by the interface trap site. From these results, irradiation variability of device is mainly caused by interface state than device itself and can be significantly minimized by interface engineering.
Biography: 1. Radiation Hardened Semiconductor Device Research and Development, especially nano-scale devices. 2. Analysis of Radiation(gamma, proton, heavy ion) Effect to Semiconductor. 3. Advanced radiation detector research and development
Two-dimensional Materials and Wide Bandgap Semiconductors: integration challenges and novel device applications
Filippo Giannazzo (CNR-IMM)
Abstract: The integration of 2D materials, like graphene and MoS 2, with wide bandgap (WBG) semiconductors (SiC, GaN and III-N alloys) is currently explored to enhance the performances of state-of-the-art WBG devices and to demonstrate innovative device concepts, including ultra-high frequency transistors, UV photodetectors, and logic devices enabling operation at high temperature and in harsh environments. This talk will review the most recent developments in this field and discuss major challenges for industrial applications of these technologies.
Biography: Filippo Giannazzo obtained his PhD in Materials Science from the University of Catania in 2002. He joined the Institute of Microelectronics and Microsystems (IMM) of CNR as a Researcher in 2006 and is Research Director from 2020. His research activities cover the following fields:
• Nanometer resolution electrical characterization methods based on scanning probe microscopy for the study of charge transport in advanced materials for micro- and nano-electronics, as well as for device reliability.
• Advanced processes (ion implantation, contacts, dielectrics) for the fabrication of high power and/or high frequency devices based on wide bandgap (WBG) semiconductors (SiC, GaN and relate group-III Nitride semiconductor).
• Integration of graphene and other 2D materials with WBG semiconductors for ultra-high-frequency (THz) and energy efficient electronic devices.
He holds several national and international collaborations with academic institutions and industries, and he has been involved in several National and European projects. In the last 10 years, he coordinated 2 EU projects (GraNitE and ETMOS) and 1 national project on the topic of 2D materials integration with GaN and SiC. He has been in the organizing committee of several international conferences/workshops, and he is frequently invited speaker. He is author or co-author of >450 papers in international peer-reviewed journals, 3 books, and 12 book chapters, and 3 patents.