(WS1) Reliability Challenges of Emerging Transistor Architectures and Materials Beyond Traditional Logic Scaling

Keywords: Vertical-channel FETs, CFETs, 3D stacked transistors, Forksheet, SiGe, germanium, amorphous oxide semiconductors, 2D materials, Carbon-Nano-Tube (CNT), HfZrO2

Introduction: As conventional transistor scaling approaches its physical and economic limits, the industry is rapidly exploring a diverse set of new materials and novel device architectures to meet future demands for performance, power efficiency, and integration density. While these innovations—such as vertical-channel FETs, CFETs, 3D stacked transistors, layout-optimized technologies (Forksheet, DTCO), and materials-driven devices (e.g., SiGe, germanium, amorphous oxide semiconductors, 2D materials, CNT, HfZrO2)—offer promising breakthroughs, they also introduce unprecedented reliability challenges. This workshop will focus exclusively on the reliability aspects of these emerging transistor technologies, providing a forum to discuss failure mechanisms, modeling complexities, and qualification strategies necessary to ensure robust deployment in advanced systems.

Proposed topics include, but are not limited to: Design and reliability implications of vertical-channel, CFET, and 3D stacked transistor architectures. Material-specific reliability concerns, including defect generation, thermal instability, and long-term degradation and correlated electron systems. Reliability modeling and assessment methodologies tailored to unconventional materials and structures. Design-Technology Co-Optimization (DTCO) strategies to mitigate reliability risks in layout-constrained and stacked transistor designs. Test and qualification approaches for emerging devices under realistic mission profiles and environmental conditions.

Moderators

(WS2) Advanced packaging to meet reliability challenges in diverse applications

Keywords: Advanced Packaging, 2.5D/3D Packaging, Al, HPC, RF, HBM, 5G, high-power devices, thermal, reliability, failures,

Introduction: Advanced packaging is vital for integrating components across applications like AI/HPC, RF, HBM, 5G, and high-power devices. Reliability challenges include addressing high-power density and heat in AI/HPC chips, dense interconnects in 2.5D/3D packages, high frequencies, and integration density in RF/5G devices, micro-bumps for HBM connectivity, and thermal expansion-induced fatigue failures due to material differences within packages, all to meet customer expectations.

Moderators

(WS3) Ensuring Reliability of Large-Scale Data Centers: An Integrated Approach from Facility, Systems to Architecture and Device Level

Keywords: Ensuring Reliability of Large-Scale Data Centers: An Integrated Approach from Facility, Systems to Architecture and Device Level

Introduction: In this workshop, experts who have ensured reliability at the device, architecture, and system levels in data center development and operations will discuss reliability assurance technologies at the system, architecture, and device levels in large-scale data centers, which have become essential for AI, particularly learning, in recent years.

In recent years, AI has been utilized in a wide range of applications, including defect detection in factories, medical image diagnosis, fraud detection in finance, customer analysis in marketing, and the generation of this workshop session introduction text. Training the large-scale generative AI foundation models required for these applications involves adjusting tens of trillions of parameters—a process that can take several months using hundreds of thousands of GPU nodes. To support the long-term stable operation of this enormous computing power, multi-layered reliability assurance is essential, extending from facility infrastructure to system configuration and even semiconductor devices.

This workshop will address the reliability monitoring/mitigation ecosystem across devices, circuits/systems and data center facilities. The discussion will involve data center level reliability such as power, cooling, telemetry and risk mitigation. Next, we will discuss architectural approaches, including redundancy configurations, failover control, and data integrity assurance. Furthermore, we will focus on device-level reliability technologies, such as semiconductor lifetime prediction, fault tolerance design, and degradation monitoring in real-world environments, and share the new challenges and solutions brought about by advanced packaging and materials technologies.

Moderators include engineers from data center operators, system vendors, and semiconductor manufacturers, who will share their knowledge and examples from their respective fields. This workshop will provide a platform to share an end-to-end perspective spanning facilities, systems, and devices, and to gain insights into achieving sustainable and highly efficient data center operations. It will be a valuable opportunity for engineers and researchers involved in reliability technology to gain practical knowledge directly applicable to both industry and research.

Moderators

(WS4): Resilient, efficient, and accurate edge AI computing with emerging memory, logic, and interconnect devices

Keywords: emerging memory, post-CMOS logic, non-volatile memory, novel interconnects, edge computing, edge AI, error mitigation techniques, beyond Moore

Introduction: Emerging artificial intelligence workloads at the edge demand complicated dataflows, including signal processing, and implementation of multiple layers of machine learning models such as convolutional, recurrent, or transformer models. These workloads are computationally demanding, creating power requirements which are particularly challenging to implement at the edge. Emerging memory, logic, and interconnect devices are poised to enable new frontiers in energy-efficiency, parallelism, and low latency in various parts of these dataflows. Yet novel devices can also often come at a severe cost in terms of resilience and accuracy. For instance, emerging logic devices may suffer from more variability than industry standard CMOS, while emerging memory devices typically do not encode weights at full precision, and may suffer from noise and drift. In the workshop, we highlight emerging approaches at the device, circuit, and architecture levels, that aim to achieve digital-equivalent performance in the presence of these challenges inherent in emerging devices. Approaches demonstrating error mitigation, calibration, and intrinsic improvements by design are welcome.

Moderators

(WS5) Wide-Bandgap Reliability Challenges: Modeling SiC and GaN Device

Keywords: SiC, GaN, Wide Bandgap (WBG) devices, Device reliability, Lifetime prediction, Accelerated stress testing

Introduction: The goal of this workshop is to foster an in-depth discussion between the SiC and GaN communities on the challenges of evaluating wide bandgap device reliability. Reliability assessment in wide-bandgap (WBG) devices is particularly complex due to the wide diversity of application environments, ranging from automotive and industrial power conversion to renewable energy systems and datacenters. These devices experience varying stress factors such as high junction temperatures, dynamic load profiles, fast switching transients, and harsh environmental conditions over their product lifetime.

Key questions remain unanswered: How to design laboratory procedures to estimate device reliability? How to link real-life operations with laboratory tests?

In SiC technologies, accelerated testing has helped to identify key degradation mechanisms, including gate oxide breakdown, threshold voltage instability, and destruction due to cosmic rays. Novel degradation processes, such as gate switching instability, have also been discovered recently. However, correlating accelerated stress data to field lifetimes remains challenging, especially under complex load cycling conditions. Moreover, the above described failure modes relate to the intrinsic device population whereas most field failures are due to extrinsics. Proper screening of extrinsics needs to be addressed.

Similarly, in GaN technologies, power switching stresses can activate trapping effects, hot-carrier degradation, and dynamic RON phenomena, which are difficult to model due to their broad range of timescales and strong dependence on operating profiles.

Although SiC and GaN devices differ in material properties and dominant failure mechanisms, they share many mission-critical reliability challenges, particularly in emerging applications like fast chargers, electric vehicles, and renewable energy systems, where long lifetimes under aggressive operating conditions are required.

This workshop aims to stimulate the discussion on lifetime prediction in WBG devices, bridging the gap between accelerated stress testing, physics-of-failure modeling, and in-field performance.

Moderators